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EtherCAT Slave Controller for

INTEGRATED CIRCUITS

TMC8462 Datasheet

Document Revision V1.5 • 2019-June-21

The TMC8462 is a complete EtherCAT

Slave Controller optimized for real time. It comprises all

blocks required for an EtherCAT slave including two 100-Mbit PHYs, a dual switch regulator power

supply and 24V capable high voltage I/Os for industrial environments. Timer, watchdog, PWM

and SPI/IIC master units allow for enhanced capabilities either in device emulation mode or in

combination with an external CPU.

Features

•

Standard compliant EtherCAT

Slave

•

Dual Integrated 100-Mbit Ethernet

PHY

• SPI Process Data Interface (PDI)

•

IO Block with 24 Multi-Function I/Os

•

Internal 3.3V plus free 5V-24V switch

regulator

•

8 High Voltage I/Os (up to 35V, 100mA)

•

Multifunction block comprises Watch-

dog, 4 PWM outputs and Step/Dir

generator

•

Direct EtherCAT access to external

ADCs, stepper motor controllers, etc.

•

EtherCAT-P compatible voltage range

Applications

• Factory Automation

• Process Automation

• Communication Modules

• Industrial IoT

• Industry 4.0

• Sensors & Encoders

• Robotics

• Industrial Motion Control

• Building Automation

Simpliﬁed Block Diagram

Terms of delivery and rights to technical change reserved.

Download newest version at: www.trinamic.com

Read entire documentation.

Summary of content (204 pages)

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INTEGRATED CIRCUITS EtherCAT Slave Controller for TMC8462 Datasheet Document Revision V1.5 • 2019-June-21 The TMC8462 is a complete EtherCAT® Slave Controller optimized for real time. It comprises all blocks required for an EtherCAT slave including two 100-Mbit PHYs, a dual switch regulator power supply and 24V capable high voltage I/Os for industrial environments.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Contents 1 Product Features 5 2 Order Codes 6 3 Principles of Operation / Key Concepts 3.1 General Device Architecture . . . . . 3.2 EtherCAT Slave Controller . . . . . . . 3.3 Multi-Function and Control IO Block . 3.4 Analog and High Voltage Block . . . . 3.5 Interfaces . . . . . . . . . . . . . . . . 3.6 Software- and Tool-Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.9 6.4.10 6.4.11 6.4.12 6.4.13 6.4.14 6.4.15 6.4.16 6.4.17 6.4.18 6.4.19 6.4.20 6.4.21 6.4.22 7 Watchdogs . . . . . . . . . . . . . . . . . . . . . SII EEPROM Interface . . . . . . . . . . . . . . . ESC Parameter RAM . . . . . . . . . . . . . . . . MII Management Interface . . . . . . . . . . . . FMMUs . . . . . . . . . . . . . . . . . . . . . . . SyncManagers . . . . . . . . . . . . . . . . . . . Distributed Clocks Receive Times . . .
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 8 9 Electrical Ratings 8.1 Absolute Maximum Ratings . . . . . . . . . . 8.2 Operational Ratings . . . . . . . . . . . . . . . 8.3 DC Characteristics and Timing Characteristics 8.3.1 High Voltage I/O Block . . . . . . . . . 8.3.2 Switching Regulators . . . . . . . . . . 8.3.3 Digital IOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 1 5 / 204 Product Features TMC8462 is an advanced EtherCAT Slave Controller device used for EtherCAT communication. It provides the interface for data exchange between EtherCAT master and the slave’s local application controller. In addition, TMC8462 provides complex IO functions paired with high voltage features and integrated 100Bit Ethernet PHYs.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 2 Order Codes Order Code Description Size TMC8462-BA TMC8462 Advanced EtherCAT® Slave Controller in 121 pin BGA package with 0.75mm pitch 9mm x 9mm TMC8462-EVAL Evaluation Board for TMC8462-BA, compatible with the modular Landungsbruecke system, RJ45 twisted pair copper interface 79mm x 85mm Landungsbruecke MCU Board 85mm x 55mm TMC8462-BOB-ETH Breakout Board (BOB) for TMC8462-BA, with 0.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 3 7 / 204 Principles of Operation / Key Concepts TMC8462 is a highly integrated ASIC providing the interface between the Ethernet-based EtherCAT real-time ﬁeld bus and the local application. Its extended digital and high voltage feature set provides additional functions to the EtherCAT slave. 3.1 General Device Architecture Figure 1 shows the general device architecture and major connections of TMC8462.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 3.2 8 / 204 EtherCAT Slave Controller TMC8462 contains a standard-conform EtherCAT Slave Controller (ESC) providing real-time EtherCAT MAC layer functionality to EtherCAT slaves. It connects via MII interface to standard Ethernet PHYs and provides a digital control interface to a local application controller while also providing the option for standalone operation. The ESC part of TMC8462 provides the following EtherCAT-related features.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 9 / 204 PWM Block The integrated PWM block provides up to 4 PWM channels. PWM frequency and duty cycle as well as polarities and dead times are conﬁgurable. The outputs can be conﬁgured for a safe state in case of emergency. Generic SPI Master Interface The TMC8462 provides a generic SPI master interface to connect to onor off-board SPI slave peripherals like ADCs, sensors, or motor drivers.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 10 / 204 Single Supply Operation TMC8462 is designed to work with a single external power supply rail. All required supply voltages are generated internally. The required external supply rail depends on the application scenario (between 3.3V and 24V). 3.5 Interfaces Field Bus Interface TMC8462 contains 2 integrated 100-Mbit Ethernet PHYs and directly connects to the ﬁeld bus using an external transformer circuit.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 11 / 204 Figure 2: TMC8462 Evaluation Board The complete board design ﬁles are available for download and can be used as reference. All information is available for download on the speciﬁc product page on TRINAMIC’s website at http://www.trinamic.com/products/integrated-circuits/evalboards. Breakout Board (BOB) Besides the Evaluation board another smaller breakout board is available.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 12 / 204 Figure 3: TMC8462 breakout board for RJ45 and TPC TRINAMIC Technology Access Package In addition, a comprehensive source code and software package – TRINAMIC Technology Access Package (TTAP) – is available for download to get started quickly with own code. The TTAP is available at https://www.trinamic.com/support/software/access-package/.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 13 / 204 The latest version and additional information is available for download from TRINAMIC’s website at http://www.trinamic.com/software-tools/tmcl-ide. EtherCAT Slave Conﬁguration Conﬁguration of the EtherCAT Slave Controller is done during boot time with conﬁguration information read from the SII EEPROM after reset or power cycling. This information must be (pre)programmed into the SII EEPROM.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Figure 6: Conﬁguration wizard example – SII EEPROM content and C-code output ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 4 4.1 Device Pin Deﬁnitions Pinout and Pin Coordinates of TMC8462-BA 1 3 2 4 5 6 7 8 9 10 11 A B C D E F G H J K L Figure 7: TMC8462-BA Pinout top view 4.2 Signal Descriptions Name Pin Type (I,O,PU,PD) Function NRESET K4 I/O Low active system reset. NRESET is an I/O pin. Connected to VCCIO via a 10K resistor and to GND via a 10nF capacitor if no other reset source for proper power-on reset is used.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Name Pin Type (I,O,PU,PD) Function RESET_OUT J4 O This high-active reset output is activated via EtherCAT register 0x0040), therefore RESET_OUT has to trigger the NRESET input, which clears RESET_OUT. This connection incl. changing the polarity has to be made externally . ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Name Pin Type (I,O,PU,PD) Function PROM_INIT J5 O Signal indicating that EEPROM has been loaded, 0 = not ready, 1 = EEPROM loaded PROM_CLK H4 O External I2C EEPROM clock signal, use 1K pull up resistor to 3.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Name Pin Type (I,O,PU,PD) Function Switching Regulator 0 IOs VS0 L7 I Switching regulator 0 supply voltage, Switching regulator 0 provides a ﬁxed 3.3V output. GND0 L9 I Switching regulator 0 ground, connect to GND SW0 L8 O Switching regulator 0 output, ﬁxed 3.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Name Pin Type (I,O,PU,PD) Function Bus Interface 1 IOs (EtherCAT OUT Port) TN1 K1 IO Negative pin of differential transmit output pair TP1 L1 IO Positive pin of differential transmit output pair RN1 G1 IO Negative pin of differential receive output pair RP1 H1 IO Positive pin of differential receive output pair REGOUT1 L2 O Regulator power output, use a 10uF and 0.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 5 5.1 Device Usage and Handling Process Data Interface The Process Data Interface (PDI) is an SPI interface with a clock frequency of up to 30 MHz. The ESC registers and the process data RAM can be accessed from an external microcontroller using this interface. The interface can be conﬁgured via the EEPROM, however it is recommended to use the default conﬁguration (SPI mode 3 with low active chip select).
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 TMC8462 pin Description Typical pin on a MCU PDI_EOF Indicates end of an Ethernet/EtherCAT frame General purpose Input PDI_WDSTATE 0: Watchdog expired; 1: Watchdog not expired General purpose Input PDI_WDTRIGGER Watchdog triggered if ’1’ General purpose Input Table 3: PDI signal description 5.1.1 SPI protocol description Each SPI datagram contains a 2- or 3-byte address/command part and a data part.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Command 6 - ADDRESS EXTENSION The address extension command is mainly used for the 3-byte addressing mode as shown in Figure 10. For SPI masters that can only process datagrams with an even number of bytes, it might be necessary to pad the datagram to an even number of bytes. This can be achieved by duplicating the third byte of the 3-byte address/command part and using the address extension command in all but the last duplicate.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 5.2 MFC IO Control Interface The MFC IO block of the TMC8462 comes with a dedicated SPI slave interface to allow direct access from a local application controller. It is called MFC CTRL SPI interface. This interface to the MFC IO block’s functions is always available, even if the EtherCAT state machine is currently not in operational state (OP). Protocol structure and timing are identical to the PDI SPI.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 28 / 204 6 6 Figure 13: MFC CTRL SPI 2 byte addressing 6 6 Figure 14: MFC CTRL SPI 3 byte addressing 5.2.2 Timing example This example shows a generic MFC register read access with wait state. The delays between the transferred bytes are just to show the byte boundaries and are not required. Figure 15: MFC SPI timing example 5.2.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 29 / 204 To share the SPI bus lines, conﬁguration pin PDI_SHARED_BUS must be pulled high as shown in the ﬁgure below. Figure 16: SPI bus sharing ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 5.3 30 / 204 Ethernet Physical Layer Connection TMC8462 comes with two integrated 100-Mbit Ethernet PHYs eliminating the need for external PHY components. The physical media interface can connect to (shielded) twisted pair copper buses ((S)TPC). Port signals with index 0 represent the EtherCAT IN port. Port signals with index 1 represent the EtherCAT OUT port.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 5.4 5.4.1 External Circuitry and Applications Examples Device Reset The NRESET signal should at least be connected to VCCIO via a 10K resistor and to GND via a 10nF capacitor if no other controlled reset source for proper power-on behavior and reset is used. VCCIO (3.3V) TMC8462 10kΩ NRESET 10nF Figure 18: Minimum external circuit for power-on reset 5.4.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 5.4.3 PHY Power Regulator Filtering The internal PHY circuits require external ﬁlter capacitors. TMC8462 REGOUT0 10µF 100nF REGOUT1 10µF 100nF Figure 20: PHY power regulator ﬁltering ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 5.4.4 External Circuit for Fixed Switching Regulator 0 Switching regulator 0 is an internal buck switching regulator and generates a ﬁxed 3.3V supply with approximately 500mA. This 3.3V supply shall be used to power VCCIO and PLLCLK_VCCIO. This regulator comes with an integrated Schottky diode which minimizes part count, when an external 5V supply is available. This 3.3V can also be used to power other on-board devices, e.g.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 5.4.5 External Circuit for Adjustable Switching Regulator 1 Switching regulator 1 is an internal buck switching regulator and generates an adjustable supply rail with approximately 500mA. The voltage at SW1 can be adjusted using a resistor network in the switching regulator’s feedback path at VOUT_FB. VOUT_FB should be at 1.2V using a resistor divider.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 5.4.6 Minimum External Supply Circuit for Single 3.3V Supply The diagram shows the minimum external circuit when using a single 3.3V supply only. Both internal switching regulators are not used in this example. Therefore, both supply ports VS0 and VS1 are not connected. The high voltage IOs are also not used in this example. Therefore, the three high voltage IO supply ports VIO1, VIO2, and VIO3 are not connected. VS=3.3V VS=3.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 5.4.7 Minimum External Supply Circuit for Single 5V Supply The diagram shows the minimum external circuit when using a single 5V supply only. Switching regulator 0 is used to generate the 3.3V for VCCIO and PLLCLK_VCCIO. Switching regulator 1 is not used in this example. Therefore, supply port VS1 is not connected. The high voltage IOs are also not used in this example.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 5.4.8 Minimum External Supply Circuit for Single Supply >5V To connect TMC8462 to a single supply greater than 5V the circuit is very similar to Figure 25. The main difference is that an additional external diode (MSS1P6) is required at output SW0. The pin SW_DIODE is open. VS>5V TMC8462 Supply VS VDD5_OUT 100nF 100nF SW1 VS0 100nF VOUT VOUT_FB VS1 3.3V GND1 4x VCCIO 3.3V 4x100nF 22µH SW0 1Ω 600 Ω @100MHz 1.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 5.4.9 Typical Power Supply Chain Using Both Buck Converters VS 5V. . . 24V VS, VS1, VIO1, VIO2, VIO3 Adj. buck converter 5V. . . 24V,
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 byte up to 16kBit to two address bytes from 32kBit. Up to 16kBit the PROM_SIZE pin must be tied to GND, above that, it must be tied to VCCIO (3.3V). 3.3V 3.3V 3.3V SII EEPROM 1k Ω 1k Ω VCC TMC8462 SII EEPROM signals GND or 3.3V PROM_SIZE PROM_CLK SCL Signal to uC PROM_INIT PROM_DATA SDA WP A2 A1 A0 GND 100nF Figure 29: SII EEPROM circuit (shown for EEPROMs >32kBit) 5.4.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6 40 / 204 EtherCAT Slave Controller Description 6.1 General EtherCAT Information TMC8462 contains a standard-conform EtherCAT Slave Controller (ESC) providing real-time EtherCAT MAC layer functionality to EtherCAT slave devices.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.2 Overview of Available Chip Features Chip Feature / Description Domain TMC8460 TMC8461 TMC8462 TMC8670 The following table shows EtherCAT chip features available in TRINAMIC’s EtherCAT slave controller solutions.
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/ 204 Chip Feature / Description Domain TMC8460 TMC8461 TMC8462 TMC8670 TMC8462 Datasheet • Document Revision V1.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.3 EtherCAT Register Overview TMC8462 has an address space of 20 KByte. The ﬁrst block of 4KByte (0x0000:0x0FFF) is reserved for the standard ESC- and EtherCAT-relevant conﬁguration and status registers. The Process Data RAM (PDRAM) starts at address 0x1000. TMC8462 has a Process Data RAM of 16 Kbyte.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4 EtherCAT Register Set 6.4.1 ESC Information 6.4.1.1 Type (0x0000) Bit Description ECAT PDI Reset Value 7:0 Type of EtherCAT controller r/- r/- TMC8460: TMC8461: TMC8462: TMC8670: 0xD0 0xD0 0xD0 0xD0 Table 9: Register 0x0000 (Type) 6.4.1.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.1.4 FMMUs supported (0x0004) Bit Description ECAT PDI Reset Value 7:0 Number of supported FMMU channels (or entities) of the EtherCAT slave controlller. r/- r/- TMC8460: TMC8461: TMC8462: TMC8670: 6 8 8 4 Table 12: Register 0x0004 (FMMUs) 6.4.1.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.1.7 Bit Port Descriptor (0x0007) Description ECAT PDI Reset Value Port conﬁguration: 00: Not implemented 01: Not conﬁgured (SII EEPROM) 10: EBUS 11: MII RMII RGMII 1:0 Port 0 r/- r/- TMC8460: TMC8461: TMC8462: TMC8670: 11 11 11 11 3:2 Port 1 r/- r/- TMC8460: TMC8461: TMC8462: TMC8670: 11 11 11 11 7:4 not supported r/- r/- 0 Table 15: Register 0x0007 (Port Descriptor) 6.4.1.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Bit Description ECAT PDI 7 Separate Handling of FCS Errors: 0: Not supported 1: Supported, frames with wrong FCS and additional nibble will be counted separately in Forwarded RX Error Counter r/- r/- 8 Enhanced DCSYNC Activation 0: Not available 1: Available NOTE: This feature refers 0x981.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.2 6.4.2.1 Station Address Conﬁgured Station Address (0x0010:0x0011) Bit Description ECAT PDI 15:0 Address used for node addressing (FPxx commands) r/w r/- Reset Value Table 17: Register 0x0010:0x0011 (Station Addr) 6.4.2.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.3 6.4.3.1 Write Protection Write Register Enable (0x0020) Bit Description ECAT PDI 0 If write register protection is enabled, this register has to be written in the same Ethernet frame (value does not care) before other writes to this station are allowed. Write protection is still active after this frame (if Write Register Protection register is not changed).
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.3.4 ESC Write Protection (0x0031) Bit Description ECAT PDI 15:0 Write protect: 0: Protection disabled 1: Protection enabled All areas are write protected, except for 0x0030. r/w r/- 7:1 Reserved, write 0 r/- r/- Table 22: Register 0x0031 (ESC Write Prot.) ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.4 6.4.4.1 Bit Data Link Layer ESC Reset ECAT (0x0040) Description ECAT PDI Reset is asserted after writing 0x52 (’R’), 0x45 (’E’), 0x53 (’S’) in this register with 3 consecutive frames. r/w r/- 1:0 Progress of the reset procedure: 01: after writing 0x52 10: after writing 0x45 (if 0x52 was written) 00: else r/w r/- 7:2 Reserved, write 0 r/- r/- Reset Value Write 7:0 Read Table 23: Register 0x0040 (ESC Reset ECAT) 6.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.4.3 ESC DL Control (0x0100:0x0103) Bit Description ECAT PDI 0 Forwarding rule: 0: EtherCAT frames are processed, Non-EtherCAT frames are forwarded without processing 1: EtherCAT frames are processed, NonEtherCAT frames are destroyed The source MAC address is changed for every frame (SOURCE_MAC[1] is set to 1 - locally administered address) regardless of the forwarding rule.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Bit Description ECAT PDI 18:16 RX FIFO Size (ESC delays start of forwarding until FIFO is at least half full).
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Bit Description ECAT PDI 14 Loop Port 3: 0: Open 1: Closed r*/- r/- 15 Communication on Port 3: 0: No stable communication 1: Communication established r*/- r/- Reset Value Table 27: Register 0x0110:0x0111 (DL Status) * Reading DL Status register from ECAT clears ECAT Event Request 0x0210.2.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.5.4 RUN LED Override (0x0138) Bit Description ECAT PDI 3:0 LED code: (FSM State) 0x0: Off (1-Init) 0x1-0xC: Flash 1x - 12x (4-SafeOp 1x) 0xD: Blinking (2-PreOp) 0xE: Flickering (3-Bootrap) 0xF: On r/w r/w 4 Enable Override: 0: Override disabled 1: Override enabled r/w r/w 7:5 Reserved, write 0 r/w r/w Reset Value Table 32: Register 0x0138 (RUN LED Override) Note 6.4.5.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.6 6.4.6.1 PDI PDI Control (0x0140) Bit Description ECAT PDI Reset Value 7:0 Process data interface: r/- r/- TMC8460, TMC8461, TMC8462, TMC8670: 0x00 0x00: Interface deactivated (no PDI) ... 0x05: SPI Slave ... 0x80: On-chip bus later EEPROM ADR 0x0000 only SPI Slave (0x05) is supported in the hardware Others: Reserved Table 34: Register 0x0140 (PDI Control) 6.4.6.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.6.4 PDI SPI Slave Conﬁguration (0x0150) The PDI conﬁguration register 0x0150 and the extended PDI conﬁguration registers 0x0152:0x0153 depend on the selected PDI. The Sync/Latch[1:0] PDI conﬁguration register 0x0151 is independent of the selected PDI. The TMC8460, TMC8461, TMC8462, and TMC8670 devices support SPI Slave PDI only.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Bit Description ECAT PDI Reset Value 5:4 SYNC1 output driver/polarity: 00: Push-Pull active low 01: Open Drain (active low) 10: Push-Pull active high 11: Open Source (active high) r/- r/- TMC8461: 10 TMC8462: 10 6 SYNC1/LATCH1 conﬁguration*: 0: LATCH1 input 1: SYNC1 output r/- r/- TMC8461: 1 TMC8462: 1 7 SYNC1 mapped to AL Event Request register 0x0220.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.7 Interrupts 6.4.7.1 ECAT Event Mask (0x0200:0x0201) Bit Description ECAT PDI 15:0 ECAT Event masking of the ECAT Event Request Events for mapping into ECAT event ﬁeld of EtherCAT frames: 0: Corresponding ECAT Event Request register bit is not mapped 1: Corresponding ECAT Event Request register bit is mapped r/w r/- Reset Value Table 40: Register 0x0200:0x0201 (ECAT Event M.) 6.4.7.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Bit Description ECAT PDI 3 AL Status event: 0: No change in AL Status 1: AL Status change (Bit is cleared by reading out AL Status 0x0130:0x0131 from ECAT) r/- r/- Mirrors values of each SyncManager Status: 0: No Sync Channel 0 event 1: Sync Channel 0 event pending 0: No Sync Channel 1 event 1: Sync Channel 1 event pending ... 0: No Sync Channel 7 event 1: Sync Channel 7 event pending r/w r/- Reserved r/- r/- 4 5 ...
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Bit Description ECAT PDI 4 SyncManager activation register (SyncManager register offset 0x6) changed: 0: No change in any SyncManager 1: At least one SyncManager changed (Bit is cleared by reading SyncManager Activation registers 0x0806 etc.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.8 Error Counters Errors are only counted if the corresponding port is enabled. 6.4.8.1 RX Error Counter[3:0] (0x0300:0x0307) Bit Description ECAT PDI 7:0 Invalid frame counter of Port y (counting is stopped when 0xFF is reached). r/ w(clr) r/- 15:8 RX Error counter of Port y (counting is stopped when 0xFF is reached). This is coupled directly to RX ERR of MII interface.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.8.4 PDI Error Counter (0x030D) Bit Description ECAT PDI 7:0 PDI Error counter (counting is stopped when 0xFF is reached). Counts if a PDI access has an interface error. r/ w(clr) r/- Reset Value Table 47: Register 0x030D (PDI Err Cnt) Note 6.4.8.5 Bit Error Counter 0x030D and Error Code 0x030E are cleared if error counter 0x030D is written. Write value is ignored (write 0).
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.8.6 Lost Link Counter[3:0] (0x0310:0x0313) Bit Description ECAT PDI 7:0 Lost Link counter of Port y (counting is stopped when 0xff is reached). Counts only if port loop is Auto. r/w(clr) r/- Reset Value Table 49: Register 0x0310:0x0313 (LL Counter) Note Only lost links at open ports are counted. Lost Link Counters 0x0310-0x0313 are cleared if one of the Lost Link Counters 0x0310-0x0313 is written.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.9 6.4.9.1 Watchdogs Watchdog Divider (0x0400:0x0401) Bit Description ECAT PDI 15:0 Watchdog Time PDI: number or basic watchdog increments (Default value with Watchdog divider 100µs means 100ms Watchdog) r/w r/- Reset Value Table 50: Register 0x0400:0x0401 (WD Divider) 6.4.9.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.9.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.9.6 Watchdog Counter PDI (0x0443) Bit Description ECAT PDI 7:0 Watchdog PDI counter (counting is stopped when 0xFF is reached). Counts if PDI Watchdog expires. r/ w(clr) r/- Reset Value Table 55: Register 0x0443 (WD Counter PDI) Note Watchdog Counters 0x0442 & 0x0443 are cleared if one of the Watchdog Counters 0x0442 & 0x0443 is written. Write value is ignored (write 0). ©2019 TRINAMIC Motion Control GmbH & Co.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.10 SII EEPROM Interface Address Length (Byte) Description SII EEPROM Interface 0x0500 1 EEPROM Conﬁguration 0x0501 1 EEPROM PDI Access State 0x0502:0x0503 2 EEPROM Control/Status 0x0504:0x0507 4 EEPROM Address 0x0508:0x050F 4/8 EEPROM Data Table 56: SII EEPROM Interface Register Overview 6.4.10.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.10.3 Bit EEPROM Control/Status (0x0502:0x0503) Description ∗2 ECAT PDI 0 ECAT write enable : 0: Write requests are disabled 1: Write requests are enabled This bit is always 1 if PDI has EEPROM control.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Bit Description ECAT PDI 14 Error Write Enable∗2 : 0: No error 1: Write Command without Write enable r/- r/- 15 Busy: 0: EEPROM Interface is idle 1: EEPROM Interface is busy r/- r/- Reset Value Table 59: Register 0x0502:0x0503 (PROM Cntrl) Note r/(w): write access depends upon the assignment of the EEPROM interface (ECAT/PDI). Write access is generally blocked if EEPROM interface is busy (0x0502.15=1).
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.10.5 EEPROM Data (0x0508:0x050F) Bit Description ECAT PDI 15:0 EEPROM Write data (data to be written to EEPROM) or EEPROM Read data (data read from EEPROM,. lower bytes) r/(w) r/[w] 63:16 EEPROM Read data (data read from EEPROM, higher bytes) r/- r/r[w] Reset Value Table 61: Register 0x0508:0x050F (PROM Data) Note r/(w): write access depends upon the assignment of the EEPROM interface (ECAT/PDI).
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.11 6.4.11.1 Byte ESC Parameter RAM MFC IO Block Conﬁguration (0x0580:0x05E1) Description Bytes MFC IO block conﬁguration vector for 96...
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.12 MII Management Interface Address Length (Byte) Description MII Management Interface 0x0510:0x0511 2 MII Management Control/Status 0x0512 1 PHY Address 0x0513 1 PHY Register Address 0x0514:0x0515 2 PHY Data 0x0516 1 MII Management ECAT Access State 0x0517 1 MII Management PDI Access State 0x0518:0x051B 4 PHY Port Status Table 63: MII Management Interface Register Overview 6.4.12.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Bit Description ECAT PDI 13 Read error: 0: No read error 1: Read error occurred (PHY or register not available) Cleared by writing to this register. r/(w) r/(w) 14 Command error: 0: Last Command was successful 1: Invalid command or write command without Write Enable Cleared with a valid command or by writing "‘00"’ to Command register bits [9:8].
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.12.3 PHY Register Address (0x0513) Bit Description ECAT PDI 4:0 Address of PHY Register that shall be read/written r/(w) r/(w) 7:5 Reserved, write 0 r/(w) r/(w) Reset Value Table 66: Register 0x0513 (PHY Register Address) Note 6.4.12.4 r/ (w): write access depends on assignment of MI (ECAT/PDI). Write access is generally blocked if Management interface is busy (0x0510.15=1).
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.12.6 MII Management PDI Access State (0x0517) Bit Description ECAT PDI 0 Access to MII management: 0: ECAT has access to MII management 1: PDI has access to MII management r/- r/(w) 1 Force PDI Access State: 0: Do not change Bit 0x0517.0 1: Reset Bit 0x0517.0 to 0 r/w r/- 7:2 Reserved, write 0 r/- r/- Reset Value Table 69: Register 0x0517 (MI PDI State) 6.4.12.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.13 FMMUs Address 0x0600:0x06FF Length (Byte) Description 16x16 FMMU[15:0] +0x0:0x3 4 Logical Start Address +0x4:0x5 2 Length +0x6 1 Logical Start bit +0x7 1 Logical Stop bit +0x8:0x9 2 Physical Start Address +0xA 1 Physical Start bit +0xB 1 Type +0xC 1 Activate +0xD:0xF 3 Reserved Table 71: FMMU Register Overview For the following registers use y as FMMU number.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.13.3 Logical Start bit (+0x6) Bit Description ECAT PDI 2:0 Logical starting bit that shall be mapped (bits are counted from least signiﬁcant bit (=0) to most signiﬁcant bit(=7) r/w r/- 7:3 Reserved, write 0 r/- r/- Reset Value Table 74: Register 0x06y6 (Log. Start Bit) 6.4.13.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.13.7 Type (+0xB) Bit Description ECAT PDI 0 0: Ignore mapping for read accesses 1: Use mapping for read accesses r/w r/- 1 0: Ignore mapping for write accesses 1: Use mapping for write accesses r/w r/- 7:2 Reserved, write 0 r/- r/- Reset Value Table 78: Register 0x06yB (FMMU Type) 6.4.13.8 Activate (+0xC) Bit Description ECAT PDI 0 0: FMMU deactivated 1: FMMU activated.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.14 SyncManagers Address Length (Byte) 0x0800:0x087F 16x8 Description SyncManager[15:0] +0x0:0x1 2 Physical Start Address +0x2:0x3 2 Length +0x4 1 Control Register +0x5 1 Status Register +0x6 1 Activate +0x7 1 PDI Control Table 81: SyncManager Register Overview For the following registers use y as SM number. See the device features on how many SMs are supported in a speciﬁc ESC device. 6.4.14.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.14.3 Control Register (+0x4) Bit Description ECAT PDI 1:0 Operation Mode: 00: Buffered (3 buffer mode) 01: Reserved 10: Mailbox (Single buffer mode) 11: Reserved r/(w) r/- 3:2 Direction: 00: Read: ECAT read access, PDI write access. 01: Write: ECAT write access, PDI read access.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Bit Description ECAT PDI 2 Reserved r/- r/- 3 Mailbox mode: mailbox status: 0: Mailbox empty 1: Mailbox full Buffered mode: reserved r/- r/- 5:4 Buffered mode: buffer status (last written buffer): 00: 1. buffer 01: 2. buffer 10: 3.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 not possible. PDI register function acknowledge by Write command is enabled: Writing this register from PDI in all SMs which have changed activation clears AL Event Request 0x0220.4. Writing to this register from PDI is possible; write value is ignored (write 0). 6.4.14.6 PDI Control (+0x7) Bit Description ECAT PDI 0 Deactivate SyncManager: Read: 0: Normal operation, SyncManager activated.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.15 Distributed Clocks Receive Times Depending on the available width of the Distributed Clocks feature the time stamp registers are either 32 bit (4 bytes) or 64 bits (8 bytes) wide. Please check the feature summary of the respective TRINAMIC ESC device. 6.4.15.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.16 Distributed Clocks Time Loop Control Unit Time Loop Control unit is usually assigned to ECAT. Write access to Time Loop Control registers by PDI (and not ECAT) depends on explicit hardware conﬁguration and on the used ESC type. Check the device features for availability. 6.4.16.1 System Time (0x0910:0x0917) Bit Description ECAT PDI 0:63 ECAT read access: Local copy of System Time when frame passed the reference clock (i.e.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.16.3 System Time Offset (0x0920:0x0927) Bit Description ECAT PDI 63:0 Difference between local time and System Time. Offset is added to the local time. r/(w) r/(w) Reset Value Table 92: Register 0x0920:0x0927 (Sys Time Offset) Note 6.4.16.4 Write access to this register depends upon ESC conﬁguration (typically ECAT, PDI only with explicit ESC conﬁguration: System Time PDI controlled).
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.16.6 Speed Counter Start (0x0930:0x0931) Bit Description ECAT PDI 14:0 Bandwidth for adjustment of local copy of System Time (larger values → smaller bandwidth and smoother adjustment) A write access resets System Time Difference (0x092C:0x092F) and Speed Counter Diff (0x0932:0x0933).
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.16.8 System Time Difference Filter Depth (0x0934) Bit Description ECAT PDI 3:0 Filter depth for averaging the received System Time deviation. A write access resets System Time Difference (0x092C:0x092F) r/(w) r/(w) 7:4 Reserved, write 0 r/- r/- Reset Value Table 97: Register 0x0934 (Sys Time Diff Filter) Note 6.4.16.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.17 6.4.17.1 Distributed Clocks Cyclic Unit Control Cyclic Unit Control (0x0980) Bit Description ECAT PDI 0 SYNC out unit control: 0: ECAT controlled 1: PDI controlled r/w r/- 3:1 Reserved, write 0 r/- r/- 4 Latch In unit 0: 0: ECAT controlled 1: PDI controlled NOTE: Always 1 (PDI controlled) if System Time is PDI controlled.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.18 6.4.18.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.18.2 Pulse Length of SYNC signals (0x0982:0x0983) Bit Description ECAT PDI Reset Value 0 Pulse length of SyncSignals (in Units of 10ns) 0: Acknowledge mode: SyncSignal will be cleared by reading SYNC[1:0] Status register r/- r/- 0, later EEPROM ADR 0x0002 Table 101: Register 0x0982:0x0983 (SYNC Pulse Length) 6.4.18.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.18.5 SYNC1 Status (0x098F) Bit Description ECAT PDI Reset Value 0 SYNC1 activation state: 0: First SYNC1 pulse is not pending 1: First SYNC1 pulse is pending r/- r/ (w ack)* 0 7:1 Reserved r/- r/ (w ack)* 0 Table 104: Register 0x098F (SYNC1 Status) * PDI register function acknowledge by Write command is disabled: Reading this register from PDI clears AL Event Request 0x0220.3.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.18.8 SYNC0 Cycle Time (0x09A0:0x09A3) Bit Description ECAT PDI Reset Value 31:0 WTime between two consecutive SYNC0 pulses in ns. 0: Single shot mode, generate only one SYNC0 pulse. r/(w) r/(w) 0 Table 107: Register 0x09A0:0x09A3 (SYNC0 Cycle Time) Note 6.4.18.9 Write to this register depends upon setting of 0x0980.0.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.19 6.4.19.1 Distributed Clocks LATCH In Unit Latch0 Control (0x09A8) Bit Description ECAT PDI Reset Value 0 Latch0 positive edge: 0: Continuous Latch active 1: Single event (only ﬁrst event active) r/(w) r/(w) 0 1 Latch0 negative edge: 0: Continuous Latch active 1: Single event (only ﬁrst event active) r/(w) r/(w) 0 7:2 Reserved, write 0 r/- r/- 0 Table 109: Register 0x09A8 (Latch0 Control) Note 6.4.19.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.19.3 Latch0 Status (0x09AE) Bit Description ECAT PDI Reset Value 0 Event Latch0 positive edge. 0: Positive edge not detected or continuous mode 1: Positive edge detected in single event mode only. Flag cleared by reading out Latch0 Time Positive Edge. r/- r/- 0 1 Event Latch0 negative edge. 0: Negative edge not detected or continuous mode 1: Negative edge detected in single event mode only.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.19.5 Latch0 Time Positive Edge (0x09B0:0x09B7) Bit Description ECAT PDI 63:0 Register captures System time at the positive edge of the Latch0 signal. r(ack)/- r/ (w ack)* Reset Value 0 Table 113: Register 0x09B0:0x09B7 (Latch0 Time Pos Edge) Note Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guarantees reading a consistent value.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.19.7 Latch1 Time Positive Edge (0x09C0:0x09C7) Bit Description ECAT PDI 63:0 Register captures System time at the positive edge of the Latch1 signal. r(ack)/- r/ (w ack)* Reset Value 0 Table 115: Register 0x09C0:0x09C7 (Latch1 Time Pos Edge) Note Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guarantees reading a consistent value.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.20 6.4.20.1 Distributed Clocks SyncManager Event Times EtherCAT Buffer Change Event Time (0x09F0:0x09F3) Bit Description ECAT PDI Reset Value 31:0 Register captures local time of the beginning of the frame which causes at least one SM to assert an ECAT event r/- r/- 0 Table 117: Register 0x09F0:0x09F3 (ECAT Buffer Change Event Time) Note 6.4.20.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.21 6.4.21.1 ESC Speciﬁc Product ID (0x0E00:0x0E07) Bit Description ECAT PDI Reset Value 63:0 Product ID r/- r/- TMC8460: TMC8461: TMC8462: TMC8670: 0x0000000001008460 0x0000000001108461 0x0000000001108461 0x0000000001008670 Table 120: Register 0x0E00:0x0E07 (Product ID) 6.4.21.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6.4.22 6.4.22.1 Process Data RAM Process Data RAM (0x1000:0xFFFF) The Process Data RAM starts at address 0x1000. The size of the Process Data RAM depends on the device. Bytes Description ECAT PDI Reset Value --- Process Data RAM (r/w) (r/w) Random/undeﬁned Table 122: Process Data RAM (0x1000:0xFFFF) Note (r/w): Process Data RAM is only accessible if EEPROM was correctly loaded (register 0x0110.0 = 1).
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7 110 / 204 MFC IO Block Description 7.1 General Information The MFC IO block includes a set of functions realized as dedicated hardware blocks. The MFC IO block offers 24 fully conﬁgurable IOs that can be used with any function of the MFC IO block. 16 low voltage IOs capable of 3.3V or 5V and 8 high voltage IOs capable of up to 24V are available. The MFC IO block functions can be used either via the MFC IO control interface (see section 5.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Figure 31: MFC IO Block Conﬁguration using the ESC Parameter RAM ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.2 MFC IO Register Overview The MFC IO block contains a range of registers dedicated to the speciﬁc sub-blocks. The registers can always be read by a microcontroller via the MFC IO Control SPI Interface. The registers can only be exclusively written by either the microcontroller via the MFC IO Control SPI Interface or by the EtherCAT master via a mapping in the ESC’s DPRAM.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Register Function Write/Read Size (Byte) Padding Bytes (see section 7.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Register Function Write/Read Size (Byte) Padding Bytes (see section 7.8) 61 unused/reserved - 0 0 62 unused/reserved - 0 0 63 SYNC1_SYNC0_EVENT_CNT R (ECAT only) 4 0 64 HVIO_CFG W 4 0 65 BUCK_CONV_CFG W 2 2 66 AL_OVERRIDE W 1 3 Table 124: MFC IO Register Overview for TMC8462-BA ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3 MFC IO Register Set 7.3.1 Incremental Encoder Interface 7.3.1.1 Register 0 – ENC_MODE Bit Description ECAT PDI 0 pol_A Required A polarity for an N channel event (0: neg., 1: pos.) r/w r/w 1 pol_B Required B polarity for an N channel event (0: neg., 1: pos.) r/w r/w 2 pol_N Deﬁnes active polarity of N (0: neg., 1: pos.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.1.2 Register 1 – ENC_STATUS Bit Description ECAT PDI 0 n_event 1: Encoder N event detected. Status bit is cleared on read: Read (R) + clear (C) This event can also be ORed into the interrupt output signal. See Register 51 and 52. r+c/- r+c/- 7:1 Reserved r/- r/- Range [Unit] Table 126: MFC IO Register 1 – ENC_STATUS 7.3.1.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.1.6 Register 5 – ENC_LATCH Bit Description ECAT PDI Range [Unit] 31:0 Encoder position X_ENC latched on N event r/- r/- −231 . . . +(231 ) − 1 Table 130: MFC IO Register 5 – ENC_LATCH ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.2 7.3.2.1 SPI Master Interface Register 6 – SPI_RX_DATA Bit Description ECAT PDI 63:0 Received data from last SPI transfer For SPI transfers with less than 64 bit, the upper bits of this register are unused r/- r/- Range [Unit] Table 131: MFC IO Register 6 – SPI_RX_DATA 7.3.2.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Bit Description ECAT PDI Range [Unit] 10:8 Trigger conﬁguration for transmission start 0002 : Start when data is written into TX register 0012 : Start on beginning of PWM cycle 0102 : Start on center of PWM cycle 0112 : Start on PWM A mark 1002 : Start on PWM B mark 1012 : Start on PWM A&B marks 1102 : reserved 1112 : Start on single trigger (Bit 15) r/w r/w 010 . . .
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.3 I2C Master Interface 7.3.3.1 Register 12 – I2C_TIMEBASE Bit Description ECAT PDI Range [Unit] 7:0 I2C_BIT_DURATION 0 = off 1 . . . 255 = 1µs . . . 255µs = 250kbit/s . . . 980bit/s -/w -/w 010 . . . 25510 [µs] Table 137: MFC IO Register 12 – I2C_TIMEBASE 7.3.3.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.3.4 Register 15 – I2C_ADDRESS Bit Description ECAT PDI 0 R/nW bit -/w -/w 7:1 Address -/w -/w Range [Unit] Table 140: MFC IO Register 15 – I2C_ADDRESS 7.3.3.5 Register 16 – I2C_DATA_R Bit Description ECAT PDI 7:0 Received data r/- r/- Range [Unit] Table 141: MFC IO Register 16 – I2C_DATA_R 7.3.3.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.4 7.3.4.1 Step and Direction Signal Generator Register 18 – SD_CH0_STEPRATE Bit Description ECAT 31:0 Signed accumulation constant c for SD_CH0. -/w This accumulation constant determines the time tSTEP between two successive steps and thereby the step frequency. The Sign (MSB) of this accumulation constant is used for the direction signal output (D0, D0n). The accumulation constant c is 2th complement. (see also Section 7.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.4.4 Register 21 – SD_CH0_STEPCOUNT Bit Description ECAT PDI Range [Unit] 31:0 Step counter for SD_CH0. Counting up/down depending on step direction. r/- r/- −231 . . . +(231 ) − 1 Table 146: MFC IO Register 21 – SD_CH0_STEPCOUNT 7.3.4.5 Register 22 – SD_CH1_STEPCOUNT Bit Description ECAT PDI Range [Unit] 31:0 Step counter for SD_CH1. Counting up/down depending on step direction. r/- r/- −231 . . .
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.4.8 Register 25 – SD_CH1_STEPTARGET Bit Description ECAT PDI Range [Unit] 31:0 Steps pulses (= distance) to be made for SD_CH1. Can be overwritten at any time. When zero, no more step pulses are generated at output S1 or S1n, Reading the register returns the remaining number of step pulses to be generated. -/w -/w 0. . . +(232 ) − 1 Table 150: MFC IO Register 25 – SD_CH1_STEPTARGET 7.3.4.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.4.11 Register 28 – SD_CH1_COMPARE Bit Description ECAT PDI Range [Unit] 31:0 Comparison value to compare with actual value of SD_CH1_STEPCOUNT. When both are equal and bit 6 in SD_CFG is set, the next step rate as conﬁgured in SD_CH1_NEXTSR will be assigned and used for SD_CH1_SR. -/w -/w −231 . . . +(231 ) − 1 Table 153: MFC IO Register 28 – SD_CH1_COMPARE 7.3.4.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.4.15 Register 32 – SD_CH2_NEXTSR Bit Description ECAT PDI Range [Unit] 31:0 Next accumulation constant that will be written to SD_CH2_STEPRATE at compare event. -/w -/w 0. . . +(232 ) − 1 Table 157: MFC IO Register 32 – SD_CH2_NEXTSR 7.3.4.16 Register 33 – SD_STEPLENGTH Bit Description ECAT PDI Range [Unit] 15:0 Conﬁgurable step pulse length for SD_CH0 in terms of 25MHz clock cycles. -/w -/w 0. . .
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.4.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.5 7.3.5.1 PWM Unit Register 36 – PWM_CFG Bit Description ECAT PDI Range [Unit] 11:0 PWM max count -/w -/w 0. . . +(212 ) − 1 15:12 unused -/w -/w 18:16 PWM ch0 chopper mode See Section 7.15 for more details. -/w -/w 19 unused -/w -/w 22:20 PWM ch1 chopper mode See Section 7.15 for more details. -/w -/w 23 unused -/w -/w 26:24 PWM ch2 chopper mode See Section 7.15 for more details.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.5.2 Register 37 – PWM1 Bit Description ECAT PDI Range [Unit] 11:0 PWM duty cycle (on time) for PWM1 -/w -/w 0. . . +(212 ) − 1 15:12 unused -/w -/w Table 162: MFC IO Register 37 – PWM1 7.3.5.3 Register 38 – PWM2 Bit Description ECAT PDI Range [Unit] 11:0 PWM duty cycle (on time) for PWM2 -/w -/w 0. . . +(212 ) − 1 15:12 unused -/w -/w Table 163: MFC IO Register 38 – PWM2 7.3.5.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Bit Description ECAT PDI 15:12 unused -/w -/w Range [Unit] Table 166: MFC IO Register 41 – PWM1_CNTRSHFT 7.3.5.7 Register 42 – PWM2_CNTRSHFT Bit Description ECAT PDI Range [Unit] 11:0 Shift value for PWM2 to shift PWM2 high side and low side signal edges with respect to the aligned PWM counter. -/w -/w 0. . . +(212 ) − 1 15:12 unused -/w -/w Table 167: MFC IO Register 42 – PWM2_CNTRSHFT 7.3.5.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.5.10 Register 45 – PWM_PULSE_B_PULSE_A Bit Description 11:0 ECAT PDI Range [Unit] Programmable trigger pulse A value with re- -/w spect to the common PWM counter. -/w 0. . . +(212 ) − 1 15:12 unused -/w -/w 27:16 Programmable trigger pulse B value with re- -/w spect to the common PWM counter. -/w 31:28 unused -/w -/w 0. . . +(212 ) − 1 Table 170: MFC IO Register 45 – PWM_PULSE_B_PULSE_A 7.3.5.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.6 7.3.6.1 General Purpose I/Os Register 47 – GPO Bit Description ECAT PDI 15:0 GPOx output values -/w -/w 31:16 GPOx safe state (when emergency input pin MFC_NES = ’0’) -/w -/w Range [Unit] Table 172: MFC IO Register 47 – GPO Note 7.3.6.2 Bits [31:24] are not available in -ES sample devices.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.7 7.3.7.1 DAC Unit Register 50 – DAC_VAL Bit Description ECAT 15:0 16 bit DAC value which is converted to a pseu- -/w dorandom binary sequence at the DAC output pin PDI -/w Table 175: MFC IO Register 50 – DAC_VAL ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.8 IRQ Control Block 7.3.8.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.8.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.9 7.3.9.1 Watchdog Register 53 – WD_TIME Bit Description ECAT PDI Range [Unit] 31:0 Watchdog time 32 bit/unsigned 0 = Watchdog off, > 0 = number of 25MHz clock cycles -/w -/w 0 . . . + (232 ) − 1 Table 178: MFC IO Register 53 – WD_TIME 7.3.9.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.9.3 Register 55 – WD_OUT_MASK_POL Bit Description ECAT PDI 23:0 WD_OUT_POL, -/w Polarity for outputs affected by watchdog action. each bit corresponds to one output line. The polarity describes the output level desired upon watchdog event. -/w 31:24 unused/reserved -/- -/- 55:32 WD_OUT_MASK, Each bit corresponds to one output line.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.9.5 Register 57 – WD_IN_MASK_POL Bit Description ECAT PDI 23:0 WD_IN_POL, Input signal levels for watchdog re-triggering. Each bit corresponds to one input line. The polarity describes the input level for signals selected by WD_IN_MASK required to re-trigger the watchdog timer. -/w -/w 31:24 unused/reserved -/- -/- 55:32 WD_IN_MASK, Each bit corresponds to one input line.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.10 7.3.10.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.10.3 Register 64 – HVIO_CFG Bit Description ECAT PDI 7:0 HV_SLOPE_SLOW With these option bits set to 1, the output slope of the MFC_HV[i] pin can be slowed down. -/w -/w 15:8 HV_WEAK_HIGH With these option bits set to 1, the high level driver strength of the MFC_HV[i-8] pin can be reduced. -/w -/w 23:16 HV_WEAK_LOW With these option bits set to 1, the low level driver strength of the MFC_HV[i-16] pin can be reduced.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.10.4 Register 65 – BUCK_CONV_CFG Bit Description ECAT PDI 1:0 B3V3_SAW_FREQ 3.3V switching regulator switching frequency (nominal values) 0 : 250kHz 1 : 125kHz 2 : 500kHz 3 : 1MHz -/w -/w 3:2 B3V3_FB_AMPL 3.3V switching regulator voltage error feedback ampliﬁcation 0 : 100% 1 : 150% 2 : 200% 3 : 50% -/w -/w 5:4 B3V3_FB_CAP 3.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.3.11 7.3.11.1 Application Layer Control Register 66 – AL_OVERRIDE Bit Description ECAT PDI 0 0 = no override 1 = override AL state -/w -/w 7:1 unused/reserved -/- -/- Range [Unit] Table 188: MFC IO Register 66 – AL_OVERRIDE Note The bit controls override conﬁguration of the 24 MFC IO output ports regarding the output port availability with respect to the actual EtherCAT Slave Controller’s AL state.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.4 SII EEPROM MFC IO Block Parameter Map This section describes the part of the EEPROM content and XML/ESI ﬁle that is used to conﬁgure the MFC IO block. MFC IO conﬁguration data is automatically loaded at startup from EEPROM to the ESC Parameter RAM starting at address 0x0580 of the the ESC register set. Therefore, this conﬁguration data has to be of Category 1.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.5 SII EEPROM MFC IO Crossbar Mapping The TMC8462 contains a full crossbar. The 24 MFC IO pins (16x Low Voltage 3.3V MFC IO pins and 8x High Voltage MFC IO pins) of the TMC8462 can be freely assigned to any signal coming from or going to the MFC IO functional blocks. Without initialization from the SII EEPROM on power up or later via PDI SPI/ECAT memory access during operation, all IOs are tri-stated. Note Certain output signals (e.g.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 151 / 204 used as inputs. No other functional MFC IO block is used in this example. The curly braces behind each MFC IO number contain the required conﬁguration value in decimal numbers according to Table 190. Figure 32: MFC IO Crossbar Example Conﬁguration ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.6 SII EEPROM MFC IO High Voltage IO (HVIO) Conﬁguration The 8 HVIO pins have additional conﬁguration options which can be set on power up from the SII EEPROM or later by SPI access to the memory.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.7 SII EEPROM MFC IO Switching Regulator Conﬁguration 3.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Bit Output 7 DISABLE - Disable Switching regulator 0 : Switching regulator enabled 1 : Switching regulator disabled Table 194: Conﬁguration bits for adjustable switching regulator ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.8 SII EEPROM MFC IO Memory Block Mapping The MFC registers can be mapped to speciﬁc memory areas to allow EtherCAT access, so that the data is directly copied between each register and the assigned memory location. This allows the operation with a less powerful application processor or even without an application processor at all in Device Emulation mode.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.9 SII EEPROM MFC IO Register Conﬁguration All MFC registers are accessible via the MFC IO Control SPI Interface. Alternatively they can be mapped into the ESC’s Process Data RAM to allow access via EtherCAT. In this case the mapped registers can only be written by the EtherCAT master. But they can still be read via MFC IO Control SPI Interface. The transfer of all enabled registers is performed in one access.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.10 157 / 204 MFC IO ESI/XML Conﬁguration Block This example shows the part of the ESI/XML conﬁguration ﬁle for EtherCAT slaves used to conﬁgure the MCF IO block directly out of the EEPROM (at power-up or reset). Therefore, the conﬁguration block must be classiﬁed as category 1 information within the EEPROM.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.11 158 / 204 MFC IO Incremental Encoder Block This function block provides input pins for incremental encoder signals (two quadrature signals and one index signal) with differential option. It has a large range of resolution settings, allowing the use of many different encoders without requiring extra calculations.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 159 / 204 Encoder Position The encoder counter ENC_X holds the current encoder position ready for read out. Different modes concerning handling of the signals A, B, and N take into account active low and active high signals as found with different types of encoders. The current encoder position can be read from MFC IO register 3. The encoder position can also be overwritten and set to a speciﬁc value.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.12 160 / 204 MFC IO SPI Master Block The SPI Master Unit provides an interface for up to four SPI slaves with a theoretically unlimited datagram length using multiple accesses. Figure 35: Block structure of SPI Master Unit The basic conﬁguration requires setting the SPI frequency/bit length, the datagram length and the SPI mode (clock polarity and phase).
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 162 / 204 5. Write Data into TX register (e.g. TMC262 DRVCONF register, all 64bit are shown) SPI_TX_DATA <= 0x00000000000EF010 6. Wait until SPI-Master is ready while (SPI_STATUS & 0x01 != 0x01) 7.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 163 / 204 6. Write Data for the last 40 outputs into TX register SPI_TX_DATA <= 0xAA5555AA55 7. Wait until SPI-Master is ready while (SPI_STATUS & 0x01 != 0x01) Chain of 10 74xx595 shift registers used as 80 digital outputs (bad example) This bad example is the same as the previous one but with the non-recommended datagram split of 64 bits + 16 bit.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 6. Use a 16 bit datagram (remaining outputs) SPI_LENGTH <= 0x0F 7. Start on TX write, SPI-Mode 3, MSB ﬁrst, Drive CS high at the end, Slave 0) SPI_CONF <= 0x0060 8. Write Data for the last 16 outputs into TX register SPI_TX_DATA <= 0xAA55 9. Wait until SPI-Master is ready while (SPI_STATUS & 0x01 != 0x01) ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.13 165 / 204 MFC IO I2C Master Block The TMC8462 I2C master allows accessing I2C slaves by writing and reading control and data registers instead of needing to take care of timing or even bit-banging through the GPIO block. Figure 36: Block structure of SPI Master Unit I2C_TIMEBASE – Bit duration in µs This register determines the I2C clock frequency by setting the duration of a single bit.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Status bit Description 7 Error Flag 6 Not Acknowledge received/sent 5 Acknowledge received/sent 4 Write to slave mode 3 Read from Slave mode 2 Transmit Address mode 1 Repeated Start condition sent 0 Start condition sent 166 / 204 Table 200: I2C status register bits Bits 0 and 1 are set after command 0x20 was successfully executed, either if the I2C bus was idle or a start condition already has been sent.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Bit Function 7 6 5 4 3 2 1 0 A6 A5 A4 A3 A2 A1 A0 R/nW Table 202: I2C Addres register I2C_DATA_R – Data register for received data After a read command, this register contains the last read data byte. I2C_DATA_W – Data register for data to transmit The data byte that should be sent with the next write command is written to this register. Basic usage An usual communication cycle is done by the following steps 1.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 168 / 204 5. Write upper byte of the memory address I2C_DATA_W <= 0x12 6. Send Data I2C_CONTROL <= 0x04 7. Write lower byte of the memory address I2C_DATA_W <= 0x34 8. Send Data I2C_CONTROL <= 0x04 9. Send Repeated-Start Condition I2C_CONTROL <= 0x20 10. Write the slave address and the R bit ((0x50 « 1) + 1 = 0xA1) I2C_ADDR <= 0xA1 11. Command: Receive Data and send ACK I2C_CONTROL <= 0x02 12.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.14 169 / 204 MFC IO Step and Direction Block The MFC IO step & direction block allows for generation of deﬁned step pulse frequencies along with a direction signal. This is done by writing an accumulation constants to a register. Toggle of the MSB of the accumulation register value generates an internal step pulse of one internal clock cycle. The direction signal is the MSB of the accumulation constant.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Figure 38: Step & Direction Signal Timing Parameter Value Description / Function Comment fCLK [Hz] 25 MHz clock frequency of step direction unit clock frequency of the step direction unit tCLK [s] 40 ns clock period length tCLK = 1/fCLK fST EP = (fCLK /232 ) ∗ (SD_CHx_ST EP RAT E) step frequency, programmed via step rate accumulation constant SD_CHx_STEPRATE fST EP [Hz] Max. fST EP [Hz] 12.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 171 / 204 Step Rate Accumulation Constant Register SD_CHx_STEPRATE The step direction accumulation constant determines the time tST EP between two successive step pulses – this is actually the step rate. Each internal PWM clock accumulates an accumulator according to a = a + c with the accumulator constant c. Toggle of the MSB of the accumulator register a triggers a step pulse.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.15 MFC IO PWM Block The MFC IO block of TMC8462 offers a 4-channel pulse width modulation (PWM) block including a programmable brake before make (BBM) unit and selection of different PWM modes. Both high side and low side control signals are available as separate outputs. A single PWM counter generates the four synchronous PWM signals. The conﬁgurable maximum count deﬁnes the PWM frequency.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Brake Before Make time tBBM with tBBM _H = BBM _H ∗ tCLK tBBM _L = BBM _L ∗ tCLK tBBM Individually programmable for high side and low side due to different timing requirements, especially when using PMOS @ High Side and NMOS @ Low Side Table 204: PWM unit parameters PWM_MAXCNT Conﬁguration This conﬁguration can be found in the PWM_CFG register. It deﬁnes the number of counts per PWM cycle for three PWM units.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 174 / 204 Figure 40: PWM chopper modes PWM Alignment Conﬁguration This conﬁguration can be found in the PWM_CFG register. It determines the alignment of the 4 PWM units. The alignment can be programmed left aligned, centered, or right aligned. All 4 channels use the same conﬁguration. ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Figure 41: PWM Timing (centered PWM) Figure 42: PWM Timing (left aligned PWM) ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 176 / 204 Figure 43: PWM Timing (right aligned PWM) PWM Polarity Conﬁguration This conﬁguration can be found in the PWM_CFG register. The PWM signals of the 4 channels are of positive logic. Logical one level means ON and logical zero level means OFF. Depending on the MOSFET drivers, switching on a MOSFET might require an inverted logical level.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 177 / 204 PWM Value Together with the programmed PWM counter length, the PWM values determine the PWM duty cycle. The PWM duty cycle is individually programmable for each of the 4 PWM channels. Trigger Pulses A and B Conﬁguration The positions of the trigger pulses A and B are programmable within the PWM cycle. These pulses can be used for different purpose, e.g., to trigger ADC sampling at a speciﬁc point in time.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.16 MFC IO DAC Block The DAC block generates a digital signal based on a 16 bit pseudo random number generator (PRNG). A pseudo random number (PRN) is compared to the desired output value and a the output is set to 1 if the PRN is lower than the output value. The PRN generator is clocked with 100MHz, which results in a period length of 655.36µs. The output signal can be ﬁltered with a simple RC lowpass.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.17 MFC IO General Purpose IO Block TMC8462 has 16 general purpose IO lines that can be freely conﬁgured and used via the 24 MFC IO low voltage and high voltage pins. The general purpose IO signals can be used for indicator LEDs, switch inputs, and even for relays or small DC motors on the HVIO pins.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.18 180 / 204 MFC IO IRQ Block The MFC_IRQ output signal is driven by the MFC IO IRQ block and can be used to indicate various events of the MFC IO block. The IRQ unit uses two registers to conﬁgure certain IRQ trigger events and to check the IRQ source when the MFC_IRQ has been triggered.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.19 181 / 204 MFC IO Watchdog Block General Function The watchdog timer allows monitoring of external signals, or monitoring of EtherCAT activity. A certain condition can be chosen for retriggering the watchdog, i.e. a certain input signal constellation. In case this constellation does not occur at least once within a pre-programmable time period, the watchdog timer will expire and will trigger a certain watchdog action.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Watchdog Register Set Once initialized, the watchdog timer monitors the application for activity and allows setting of pre-programmed I/O patterns, in case the time limit is expired without activity. In order to allow tuning of this time limit, the maximum time between two trigger events becomes measured. This function also allows delay time measurement for input channels (i.e. when no watchdog action is chosen).
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.20 185 / 204 MFC IO Emergency Switch Input The MFC IO block offers a dedicated emergency switch input called MFC_NES. It is low active. It is used to set speciﬁc MFCIOxx outputs to a a conﬁgurable safe state in case of emergency. The MFC_NES pin has weak internal pull-down resistor. A microcontroller or another circuit must actively drive a high level at MFC_NES for normal operation.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 7.21 MFC IO Analog and High Voltage Block 7.21.1 Multi Voltage High Current I/O Lines MFC_HVy differential HV or slow slope INx MFCIOx.slope MFCIOx.differential Input control block 1/2 VIOx SLOPE Q S R low voltage & fast slope 17/40 VIOx 0.3V hyst. 1µs 1.2V VIOx VIOx MFCIOx.hv_on 5.5V SLOPE 100µA Level shifter OUTx OEx MFCIOx.weak_h MFCIOx.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Upon exceeding the activation threshold, a time proportional to the excess current is required to switch off the output. This way, short time peak currents can safely be switched, e.g. when long cables or capacitive loads are attached. An interrupt ﬂag informs about an active overcurrent condition. The short condition will be cleared once the output polarity is toggled.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 +VS Undervolt VS Bandgap and 5V auxiliary regulator 1.2V Ref 100nF VDD5_OUT 470nF Regulator 1 / 3.3V Regulator Switch reg supply VDD5_INx VSx SC_DETECT 100nF IMAX SC_DISABLE Set SAW_FREQ[1..0] SAW oscillator Dutycycle limit 1 MOSFET PMOS Driver S Q SWx R SWx_IN + LSW Reg. 1 only VOUT1_DAMP SW regulator output 3.3VRegulatoronly FB_CAP[1..0] - FB_AMPL[1..
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 • over-temperature detection for the HV IO circuit • short circuit/over-current detection for the switching regulators • over-temperature detection for the adjustable switching regulator Please refer to Table 184 for more details. ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 8 Electrical Ratings 8.1 Absolute Maximum Ratings Note The maximum ratings may not be exceeded under any circumstances. Operating the circuit at or near more than one maximum rating at a time for extended periods shall be avoided by application design. Parameter Symbol Supply and HV IO supply voltage with TJ = 0°C *) Min Max Unit VVS , VVIOx 40 V Supply and HV IO supply voltage max.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 8.2 Operational Ratings Parameter Symbol Min Max Unit Junction temperature TJ -40 125 °C High voltage supply voltage VVS,VS0,VS1 4.75 34 V Digital I/O 3.3V supply voltage VVCCIO 3.15 3.45 V I/O supply voltage (high voltage mode) VVIOx 6.0 34 V I/O Supply voltage (low voltage mode) VVIOx 3.0 5.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Parameter Symbol Conditions RDSon power switch RON TJ =25 °C Over-current protection activation threshold sourcing IOCH Output sourcing current Oscillator frequency fOSC Setting 00 (default) 240 Setting 01 130 Setting 10 470 Setting 11 890 Duty cycle limit dl Schottky diode forward voltage VSDF Min 800 Typ Max Unit 1 1.5 Ω 1200 1600 mA kHz 83 I=350mA 0.60 Soft startup time % 0.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 9 9.1 Manufacturing Data Package Dimensions Figure 53: TMC8462-BA package outline drawing ©2019 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany Terms of delivery and rights to technical change reserved. Download newest version at www.trinamic.
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 Symbol Min Normal Max Total thickness A — — 1.4 Stand off A1 0.27 — 0.37 Substrate thickness A2 0.26 REF Mold thickness A3 0.7 REF Body size D 9 BSC Body size E 9 BSC Ball diameter 0.4 Ball Opening 0.3 Ball width b Ball pitch Ball count — 0.47 e 0.75 BSC n 121 Edge ball center to center D1 7.5 BSC Edge ball center to center E1 7.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 9.2 196 / 204 Marking The device marking is shown below. Pin 1 location is highlighted with a dot. YYWW = date code. LLLLL = Lot number. Figure 54: TMC8462-BA device marking 9.3 Board and Layout Considerations • Example part libraries for different CAD tools are available as downloads on the respective IC product page on the TRINAMIC website at https://www.trinamic.com/products/integrated-circuits/.
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 11 11.1 199 / 204 TMC8462-BA Errata Case 1 – Lost Link Counters Description The TMC8462 features lost link error counters for each of the two MII ports. The Lost Link Counters can be read from ESC addresses 0x0310 and 0x0311. See also Section 6.4.8.6. The observed behavior is that after reset and after power cycling each counter already shows a value of 1 (one) but it should be 0 (zero).
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 200 / 204 Figures Index General device architecture . . . . . . . TMC8462 Evaluation Board . . . . . . . TMC8462 breakout board for RJ45 and TPC . . . . . . . . . . . . . . . . . . . . . TMCL-IDE . . . . . . . . . . . . . . . . . . Conﬁguration wizard example – MFC IO block conﬁguration . . . . . . . . . . . .
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Tables Index TMC8462 order codes . . . . . . . . . Pin and Signal description for TMC8462-BA . . . . . . . . . . . . . . . PDI signal description . . . . . . . . . . PDI SPI commands . . . . . . . . . . . MFC CTRL SPI signal description . . .
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 Register 0x0930:0x931 (Speed Cnt Start) 96 Register 0x0932:0x0933 (Speed Cnt Diff) 96 Register 0x0934 (Sys Time Diff Filter) . 97 Register 0x0935 (Speed Cnt Filter Depth) 97 Register 0x0980 (Cyclic Unit Cntrl) . .
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/ 204 TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 MFC IO Register 57 – WD_IN_MASK_POL138 MFC IO Register 58 – WD_MAX . . . . 138 MFC IO Register 59 – HV_ANA_STATUS 139 MFC IO Register 63 – SYNC1_SYNC0_EVENT_CNT . . . . . . 139 MFC IO Register 64 – HVIO_CFG . . . . 140 MFC IO Register 65 – BUCK_CONV_CFG 142 MFC IO Register 66 – AL_OVERRIDE . . 143 EEPROM Parameter Map . . . . . . . .
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TMC8462 Datasheet • Document Revision V1.5 • 2019-June-21 14 204 / 204 Revision History 14.1 IC Revision Version Date Author Description V1.0 01.07.2016 SK, SL, BD, HS Silicon V1.0 V1.1 01.09.2017 SK, SL, BD, HS Silicon V1.1 V1.11 01.11.2017 SK, SL, BD, HS Silicon V1.11 Table 218: IC Revision 14.2 Document Revision Version Date Author Description V1.00 01.09.2017 SK, SL, BD Initial release version V1.10 01.12.2017 SK, SL, BD Updated for ﬁnal product version V1.20 19.03.