Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)

Table 103: Register Receive Time Latch Mode (0x0936)

Bit

Description

ECAT PDI Reset Value

0 Receive Time Latch Mode:

0: Forwarding mode (used if frames are

entering the ESC at port 0 first):

Receive time stamps of ports 1-3 are

enabled after the write access to

0x0900, so the following frame at ports

1-3 will be time stamped (this is

typically the write frame to 0x0900

coming back from the network behind

the ESC).

1: Reverse mode (used if frames are

entering ESC at port 1-3 first):

Receive time stamps of ports 1-3 are

immediately taken over from the

internal hidden time stamp registers, so

the previous frame entering the ESC at

ports 1-3 will be time stamped when

the write frame to 0x0900 enters port 0

(the previous frame at ports 1-3 is

typically the write frame to 0x0900

coming from the master, which will

enable time stamping at the ESC once it

enters port 0).

r/w

r/- 0

7:1 Reserved r/- r/- 0

NOTE: There should not be frames traveling around the network before and after the time stamps are taken,

otherwise these frames might get time stamped, and not the write frame to 0x0900.