Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 95
Table 97: Register System Time Delay (0x0928:0x092B)
Bit
Description
ECAT PDI Reset Value
31:0 Delay between Reference Clock and the ESC r/(w) r/(w) 0
NOTE: Write access to this register depends upon ESC configuration (typically ECAT, PDI only with explicit ESC
configuration: System Time PDI controlled). Reset internal system time difference filter and speed counter filter by
writing Speed Counter Start (0x0930:0x0931) after changing this value.
Table 98: Register System Time Difference (0x092C:0x092F)
Bit
Description
ECAT PDI Reset Value
30:0
Mean difference between local copy of
System Time and received System Time
values
r/-
r/- 0
31
0: Local copy of System Time greater than
or equal received System Time
1: Local copy of System Time smaller than
received System Time
r/-
r/- 0
Table 99: Register Speed Counter Start (0x0930:0x931)
Bit
Description
ECAT PDI Reset Value
14:0 Bandwidth for adjustment of local copy of
System Time (larger values → smaller
bandwidth and smoother adjustment)
A write access resets System Time Difference
(0x092C:0x092F) and Speed Counter Diff
(0x0932:0x0933).
Minimum value: 0x0080 to 0x3FFF
r/(w) r/(w) 0x1000
15 Reserved, write 0 r/- r/- 0
NOTE: Write access to this register depends upon ESC configuration (typically ECAT, PDI only with explicit ESC
configuration: System Time PDI controlled).
Table 100: Register Speed Counter Diff (0x0932:0x933)
Bit
Description
ECAT PDI Reset Value
15:0 Representation of the deviation between local
clock period and Reference Clock’s clock period
(representation: two’s complement)
Range: ±(Speed Counter Start – 0x7F)
r/- r/- 0x0000
NOTE: Calculate the clock deviation after System Time Difference has settled at a low value as follows:
2)DiffCounterSpeedStartCounter2)(SpeedDiffCounterSpeedStartCounter(Speed5
DiffCounterSpeed
Deviation
+−++
=