Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 90
Table 89: Register Status Register SyncManager y (0x0805+y*8)
Bit
Description
ECAT PDI Reset Value
0
Interrupt Write:
1: Interrupt after buffer was completely
and successfully written
0: Interrupt cleared after first byte of
buffer was read
NOTE: This interrupt is signaled to the reading
side if enabled in the SM Control register.
r/-
r/- 0
1
Interrupt Read:
1: Interrupt after buffer was completely
and successful read
0: Interrupt cleared after first byte of
buffer was written
NOTE: This interrupt is signaled to the writing side
if enabled in the SM Control register.
r/-
r/- 0
2
Reserved
r/-
r/- 0
3
Mailbox mode: mailbox status:
0: Mailbox empty
1: Mailbox full
Buffered mode: reserved
r/-
r/- 0
5:4 Buffered mode: buffer status (last written
buffer):
00: 1. buffer
01: 2. buffer
10: 3. buffer
11: (no buffer written)
Mailbox mode: reserved
r/-
r/- 11
6
Read buffer in use (opened)
r/-
r/- 0
7
Write buffer in use (opened)
r/-
r/- 0