Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 86
5.48 FMMU (0x0600:0x06FF)
Each FMMU entry is described in 16 Bytes from 0x0600:0x060F to 0x06F0:0x06FF.
y is the FMMU index.
The TMC8460-BI supports up to 6 FMMUs. Thus TMC8460-BI supports y=0…5.
Table 75: FMMU Register overview
Register Address Offset
Length
(Byte)
Description
+0x0:0x3
4
Logical Start Address
+0x4:0x5
2
Length
+0x6
1
Logical Start bit
+0x7
1
Logical Stop bit
+0x8:0x9
2
Physical Start Address
+0xA
1
Physical Start bit
+0xB
1
Type
+0xC
1
Activate
+0xD:0xF
3
Reserved
Table 76: Register Logical Start address FMMU y (0x06y0:0x06y3)
Bit
Description
ECAT PDI Reset Value
31:0 Logical start address within the EtherCAT
Address Space.
r/w r/- 0
Table 77: Register Length FMMU y (0x06y4:0x06y5)
Bit
Description
ECAT PDI Reset Value
15:0 Offset from the first logical FMMU Byte to the
last FMMU Byte + 1 (e.g., if two bytes are used
then this parameter shall contain 2)
r/w r/- 0
Table 78: Register Start bit FMMU y in logical address space (0x06y6)
Bit
Description
ECAT PDI Reset Value
2:0 Logical starting bit that shall be mapped (bits
are counted from least significant bit (=0) to
most significant bit(=7)
r/w r/- 0
7:3 Reserved, write 0 r/- r/- 0
Table 79: Register Stop bit FMMU y in logical address space (0x06y7)