Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)

5.47 Parameter RAM (0x0580:0x05AB) for TMC8460 MFCIO Block Configuration

The content of these registers can be automatically loaded from EEPROM after reset/power-up.

Therefore, the configuration date in the EEPROM must contain a section with category 1 and the

appropriate configuration vector.

There are 44 MFCIO registers. Each byte configures one of the MFCIO registers.

y is in the range of 0 to 43 and is used as offset with respect to address 0x0580.

Table 74:MFCIO Register Configuration (0x0580+

)

Bit

Description

ECAT PDI Reset Value

3:0 Update trigger selection for the respective

MFCIO register

r/w r/w 0

4 0: ECAT mapping disabled, general read/write

access only via MFC CTRL SPI to/from MCU

1: ECAT mapping enabled, general write access

only from ECAT master using configured

SyncManager, always readable by MCU via MFC

CTRL SPI

r/w r/w 0

7:5 reserved 0

When (re)configuring the EEPROM from an EtherCAT master system special care must be taken. Not

every master allows writing a category 1 entry to the EEPROM. There are different ways to write this

into the EEPROM for automatically loading the MFCIO block configuration at power-up:

• Use preprogrammed EEPROMs.

• Use a different category, e.g., 2049, first. Then overwrite the upper byte with 0 with a single

EEPROM byte write.

• Use the local microcontroller (if available) and have it connected to the EEPROM via I2C. Hold the

TMC8460 in reset while programming the EEPROM first. Afterwards tristate the local I2C bus so

that the TMC8460 has control over the IC2 interface and release the TMC8460 from reset.