Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 83
Table 68: Register PHY Address (0x0512)
Bit
Description
ECAT PDI Reset Value
4:0 PHY Address r/(w) r/(w) 0
6:5 Reserved, write 0 r/- r/-
7 Show configured PHY address of port 0-3 in
register 0x0510[7:3]. Select port x with bits
[4:0] of this register (valid values are 0-3):
0: Show address of port 0 (offset)
1: Show individual address of port x
r/(w)
r/(w) 0
NOTE: r/ (w): write access depends on assignment of MI (ECAT/PDI). Write access is generally blocked if
Management interface is busy (0x0510.15=1).
Table 69: Register PHY Register Address (0x0513)
Bit
Description
ECAT PDI Reset Value
4:0 Address of PHY Register that shall be
read/written
r/(w) r/(w) 0
7:5 Reserved, write 0 r/- r/- 0
NOTE: r/ (w): write access depends on assignment of MI (ECAT/PDI). Write access is generally blocked if
Management interface is busy (0x0510.15=1).
Table 70: Register PHY Data (0x0514:0x0515)
Bit
Description
ECAT PDI Reset Value
15:0 PHY Read/Write Data r/(w) r/(w) 0
NOTE: r/ (w): write access depends on assignment of MI (ECAT/PDI). Access is generally blocked if Management
interface is busy (0x0510.15=1).
Table 71: Register MII Management ECAT Access State (0x0516)
Bit
Description
ECAT PDI Reset Value
0
Access to MII management:
0: ECAT enables PDI takeover of MII
management control
1: ECAT claims exclusive access to MII
management
r/(w)
r/- 0
7:1
Reserved, write 0
r/-
r/- 0
NOTE: r/ (w): write access is only possible if 0x0517.0=0.