Datasheet
TMC8460-BI Datasheet (V100 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 82
Table 67: Register MII Management Control/Status (0x0510:0x0511)
Bit
Description
ECAT PDI Reset Value
0
Write enable*:
0: Write disabled
1: Write enabled
This bit is always 1 if PDI has MI control.
r/(w) r/- 0
1 Management Interface can be controlled by
PDI (registers 0x0516-0 x0517):
0: Only ECAT control
1: PDI control possible
r/-
r/-
TMC8460: 1
2 MI link detection (link configuration, link
detection, registers 0x0518-0x051B):
0: Not available
1: MI link detection active
r/-
r/-
TMC8460: 0
7:3 PHY address of port 0 r/- r/-
TMC8460: Depends on
configuration
9:8
Command register*
:
Write: Initiate command.
Read: Currently executed command
Commands:
00: No command/MI idle (clear error bits)
01: Read
10: Write
Others: Reserved/invalid commands (do not
issue)
r/(w)
r/(w)
0
12:10
Reserved, write 0
r/-
r/- 0
13
Read error:
0: No read error
1: Read error occurred (PHY or register not
available)
Cleared by writing to this register.
r/(w) r/(w) 0
14
Command error:
0: Last Command was successful
1: Invalid command or write command
without Write Enable
Cleared with a valid command or by writing
“00” to Command register bits [9:8].
r/-
r/- 0
15
Busy:
0: MI control state machine is idle
1: MI control state machine is active
r/-
r/- 0
NOTE: r/ (w): write access depends on assignment of MI (ECAT/PDI). Write access is generally blocked if
Management interface is busy (0x0510.15=1).
* Write enable bit 0 is self-clearing at the SOF of the next frame (or at the end of the PDI access), Command bits
[9:8] are self-clearing after the command is executed (Busy ends). Writing “00” to the command register will also
clear the error bits [14:13]. The Command bits are cleared after the command is executed.