Datasheet
TMC8460-BI Datasheet (V100 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 8
T
ABLE
83:
R
EGISTER
A
CTIVATE
FMMU
Y
(0
X
06
Y
C) .............................................................................................................. 87
T
ABLE
84:
R
EGISTER
R
ESERVED
FMMU
Y
(0
X
06
Y
D:0
X
06
Y
F) ............................................................................................... 87
T
ABLE
85:
S
YNC
M
ANAGER
R
EGISTER OVERVIEW
.................................................................................................................... 88
T
ABLE
86:
R
EGISTER PHYSICAL
S
TART
A
DDRESS
S
YNC
M
ANAGER Y
(0
X
0800+
Y
*8:0
X
0801+
Y
*8) ....................................... 88
T
ABLE
87:
R
EGISTER
L
ENGTH
S
YNC
M
ANAGER Y
(0
X
0802+
Y
*8:0
X
0803+
Y
*8) ...................................................................... 88
T
ABLE
88:
R
EGISTER
C
ONTROL
R
EGISTER
S
YNC
M
ANAGER Y
(0
X
0804+
Y
*8)......................................................................... 89
T
ABLE
89:
R
EGISTER
S
TATUS
R
EGISTER
S
YNC
M
ANAGER Y
(0
X
0805+
Y
*8) ........................................................................... 90
T
ABLE
90:
R
EGISTER
A
CTIVATE
S
YNC
M
ANAGER Y
(0
X
0806+
Y
*8) ........................................................................................ 91
T
ABLE
91:
R
EGISTER
PDI
C
ONTROL
S
YNC
M
ANAGER Y
(0
X
0807+
Y
*8) ................................................................................. 92
T
ABLE
92:
R
EGISTER
R
ECEIVE
T
IME
P
ORT
0
(0
X
0900:0
X
0903) ............................................................................................ 92
T
ABLE
93:
R
EGISTER
R
ECEIVE
T
IME
P
ORT
1
(0
X
0904:0
X
0907) ............................................................................................ 92
T
ABLE
94:
R
EGISTER
R
ECEIVE
T
IME
ECAT
P
ROCESSING
U
NIT
(0
X
0918:0
X
091F) ............................................................... 92
T
ABLE
95:
R
EGISTER
S
YSTEM
T
IME
(0
X
0910:0
X
0913
[0
X
0910:0
X
0917]) ........................................................................... 94
T
ABLE
96:
R
EGISTER
S
YSTEM
T
IME
O
FFSET
(0
X
0920:0
X
0923
[0
X
0920:0
X
0927]) .............................................................. 94
T
ABLE
97:
R
EGISTER
S
YSTEM
T
IME
D
ELAY
(0
X
0928:0
X
092B) .............................................................................................. 95
T
ABLE
98:
R
EGISTER
S
YSTEM
T
IME
D
IFFERENCE
(0
X
092C:0
X
092F) ..................................................................................... 95
T
ABLE
99:
R
EGISTER
S
PEED
C
OUNTER
S
TART
(0
X
0930:0
X
931) ............................................................................................ 95
T
ABLE
100:
R
EGISTER
S
PEED
C
OUNTER
D
IFF
(0
X
0932:0
X
933) ............................................................................................ 95
T
ABLE
101:
R
EGISTER
S
YSTEM
T
IME
D
IFFERENCE
F
ILTER
D
EPTH
(0
X
0934) ......................................................................... 96
T
ABLE
102:
R
EGISTER
S
PEED
C
OUNTER
F
ILTER
D
EPTH
(0
X
0935) ......................................................................................... 96
T
ABLE
103:
R
EGISTER
R
ECEIVE
T
IME
L
ATCH
M
ODE
(0
X
0936) .............................................................................................. 97
T
ABLE
104:
R
EGISTER
C
YCLIC
U
NIT
C
ONTROL
(0
X
0980) ...................................................................................................... 98
T
ABLE
105:
R
EGISTER
A
CTIVATION REGISTER
(0
X
0981) ....................................................................................................... 99
T
ABLE
106:
R
EGISTER
P
ULSE
L
ENGTH OF
S
YNC
S
IGNALS
(0
X
0982:0
X
983) ........................................................................... 99
T
ABLE
107:
R
EGISTER
A
CTIVATION
S
TATUS
(0
X
0984) ......................................................................................................... 99
T
ABLE
108:
R
EGISTER
SYNC0
S
TATUS
(0
X
098E) ............................................................................................................... 100
T
ABLE
109:
R
EGISTER
SYNC1
S
TATUS
(0
X
098F) ............................................................................................................... 100
T
ABLE
110:
R
EGISTER
S
TART
T
IME
C
YCLIC
O
PERATION
(0
X
0990:0
X
0993
[0
X
0990:0
X
0997]) ........................................ 100
T
ABLE
111:
R
EGISTER
N
EXT
SYNC1
P
ULSE
(0
X
0998:0
X
099B
[0
X
0998:0
X
099F]) ........................................................... 101
T
ABLE
112:
R
EGISTER
SYNC0
C
YCLE
T
IME
(0
X
09A0:0
X
09A3).......................................................................................... 101
T
ABLE
113:
R
EGISTER
SYNC1
C
YCLE
T
IME
(0
X
09A4:0
X
09A7).......................................................................................... 101
T
ABLE
114:
R
EGISTER
L
ATCH
0
C
ONTROL
(0
X
09A8) ............................................................................................................ 102
T
ABLE
115:
R
EGISTER
L
ATCH
1
C
ONTROL
(0
X
09A9) ............................................................................................................ 102
T
ABLE
116:
R
EGISTER
L
ATCH
0
S
TATUS
(0
X
09AE) ............................................................................................................... 103
T
ABLE
117:
R
EGISTER
L
ATCH
1
S
TATUS
(0
X
09AF) ............................................................................................................... 103
T
ABLE
118:
R
EGISTER
L
ATCH
0
T
IME
P
OSITIVE
E
DGE
(0
X
09B0:0
X
09B3
[0
X
09B0:0
X
09B7]) ........................................... 104
T
ABLE
119:
R
EGISTER
L
ATCH
0
T
IME
N
EGATIVE
E
DGE
(0
X
09B8:0
X
09BB
[0
X
09B8:0
X
09BF]) ......................................... 104
T
ABLE
120:
R
EGISTER
L
ATCH
1
T
IME
P
OSITIVE
E
DGE
(0
X
09C0:0
X
09C3
[0
X
09C0:0
X
09C7]) ........................................... 105
T
ABLE
121:
R
EGISTER
L
ATCH
1
T
IME
N
EGATIVE
E
DGE
(0
X
09C8:0
X
09CB
[0
X
09C8:0
X
09CF]) .......................................... 105
T
ABLE
122:
R
EGISTER
E
THER
CAT
B
UFFER
C
HANGE
E
VENT
T
IME
(0
X
09F0:0
X
09F3) .......................................................... 106
T
ABLE
123:
R
EGISTER
PDI
B
UFFER
S
TART
E
VENT
T
IME
(0
X
09F8:0
X
09FB) ...................................................................... 106
T
ABLE
124:
R
EGISTER
PDI
B
UFFER
C
HANGE
E
VENT
T
IME
(0
X
09FC:0
X
09FF) .................................................................... 106
T
ABLE
125:
R
EGISTER
P
RODUCT
ID
(0
X
0E00:0
X
0E07) ...................................................................................................... 107
T
ABLE
126:
R
EGISTER
V
ENDOR
ID
(0
X
0E08:0
X
0E0F) ........................................................................................................ 107
T
ABLE
127:
U
SER
RAM
(0
X
0F80:0
X
0FFF) .......................................................................................................................... 107
T
ABLE
128:
P
ROCESS
D
ATA
RAM
(0
X
1000:0
X
4FFF) .......................................................................................................... 108
T
ABLE
129:
MFCIO
B
LOCK
ECAT
W
RITE
D
ATA
M
EMORY
B
LOCK
(0
X
4000:0
X
405F) ....................................................... 108
T
ABLE
130:
P
ADDING BYTES
................................................................................................................................................. 109
T
ABLE
131:
MFCIO
B
LOCK
ECAT
R
EAD
D
ATA
M
EMORY
B
LOCK
(0
X
4800:0
X
4823) ......................................................... 110
T
ABLE
132:
P
ADDING BYTES
................................................................................................................................................. 110
T
ABLE
133
:
MFCIO
B
LOCK
R
EGISTER
O
VERVIEW
.............................................................................................................. 112
T
ABLE
134
:
EEPROM
P
ARAMETER
M
AP
&
ESC
RAM
A
DDRESS
M
APPING FOR
TMC8460-BI ....................................... 113
T
ABLE
135
:
MFCIO
REGISTER CONFIGURATION BYTE
........................................................................................................ 114
T
ABLE
136
:
MFCIO
REGISTER
S
HADOW TRIGGER SOURCE CONFIGURATION
..................................................................... 114
T
ABLE
137
:
MFCIO
INCREMENTAL ENCODER UNIT SIGNALS
............................................................................................... 121
T
ABLE
138
:
MFCIO
INCREMENTAL ENCODER UNIT REGISTER SET
....................................................................................... 121