Datasheet
TMC8460-BI Datasheet (V100 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 7
T
ABLE
27:
R
EGISTER
ESC
R
ESET
PDI
(0
X
0041) ................................................................................................................... 60
T
ABLE
28:
R
EGISTER
ESC
DL
C
ONTROL
(0
X
0100:0
X
0103) .................................................................................................. 61
T
ABLE
29:
R
EGISTER
P
HYSICAL
R
EAD
/W
RITE
O
FFSET
(0
X
0108:0
X
0109) ............................................................................ 62
T
ABLE
30:
R
EGISTER
ESC
DL
S
TATUS
(0
X
0110:0
X
0111) ..................................................................................................... 63
T
ABLE
31:
D
ECODING PORT STATE IN
ESC
DL
S
TATUS REGISTER
0
X
0111
(
TYPICAL MODES ONLY
) ................................... 64
T
ABLE
32:
R
EGISTER
AL
C
ONTROL
(0
X
0120:0
X
0121) ........................................................................................................... 65
T
ABLE
33:
R
EGISTER
AL
S
TATUS
(0
X
0130:0
X
0131) ............................................................................................................. 65
T
ABLE
34:
R
EGISTER
AL
S
TATUS
C
ODE
(0
X
0134:0
X
0135) ................................................................................................... 66
T
ABLE
35:
R
EGISTER
RUN
LED
O
VERRIDE
(0
X
0138) ............................................................................................................ 66
T
ABLE
36:
R
EGISTER
ERR
LED
O
VERRIDE
(0
X
0139) ............................................................................................................. 67
T
ABLE
37:
R
EGISTER
PDI
C
ONTROL
(0
X
0140) ...................................................................................................................... 67
T
ABLE
38:
R
EGISTER
ESC
C
ONFIGURATION
(0
X
0141) .......................................................................................................... 68
T
ABLE
39:
R
EGISTER
PDI
I
NFORMATION
(0
X
014E:0
X
014F) ................................................................................................ 69
T
ABLE
40:
R
EGISTER
PDI
SPI
S
LAVE
C
ONFIGURATION
(0
X
0150) ....................................................................................... 69
T
ABLE
41:
R
EGISTER
PDI
SPI
S
LAVE EXTENDED CONFIGURATION
(0
X
0152:0
X
0153) ........................................................ 70
T
ABLE
42:
R
EGISTER
S
YNC
/L
ATCH
[1:0]
PDI
C
ONFIGURATION
(0
X
0151) ............................................................................ 70
T
ABLE
43:
R
EGISTER
ECAT
E
VENT
M
ASK
(0
X
0200:0
X
0201) ................................................................................................ 71
T
ABLE
44:
R
EGISTER
PDI
AL
E
VENT
M
ASK
(0
X
0204:0
X
0207)............................................................................................. 71
T
ABLE
45:
R
EGISTER
ECAT
E
VENT
R
EQUEST
(0
X
0210:0
X
0211) ........................................................................................... 72
T
ABLE
46:
R
EGISTER
AL
E
VENT
R
EQUEST
(0
X
0220:0
X
0223) ................................................................................................ 72
T
ABLE
47:
R
EGISTER
RX
E
RROR
C
OUNTER
P
ORT Y
(0
X
0300+
Y
*2:0
X
0301+
Y
*2) ................................................................. 74
T
ABLE
48:
R
EGISTER
F
ORWARDED
RX
E
RROR
C
OUNTER
P
ORT Y
(0
X
0308+
Y
) ..................................................................... 74
T
ABLE
49:
R
EGISTER
ECAT
P
ROCESSING
U
NIT
E
RROR
C
OUNTER
(0
X
030C) ........................................................................ 74
T
ABLE
50:
R
EGISTER
PDI
E
RROR
C
OUNTER
(0
X
030D) .......................................................................................................... 74
T
ABLE
51:
R
EGISTER
SPI
PDI
E
RROR
C
ODE
(0
X
030E) ......................................................................................................... 74
T
ABLE
52:
R
EGISTER
L
OST
L
INK
C
OUNTER
P
ORT Y
(0
X
0310+
Y
) ........................................................................................... 75
T
ABLE
53:
R
EGISTER
W
ATCHDOG
D
IVIDER
(0
X
0400:0
X
0401) ............................................................................................. 75
T
ABLE
54:
R
EGISTER
W
ATCHDOG
T
IME
PDI
(0
X
0410:0
X
0411) .......................................................................................... 75
T
ABLE
55:
R
EGISTER
W
ATCHDOG
T
IME
P
ROCESS
D
ATA
(0
X
0420:0
X
0421) ......................................................................... 75
T
ABLE
56:
R
EGISTER
W
ATCHDOG
S
TATUS
P
ROCESS
D
ATA
(0
X
0440:0
X
0441) .................................................................... 76
T
ABLE
57:
R
EGISTER
W
ATCHDOG
C
OUNTER
P
ROCESS
D
ATA
(0
X
0442) ................................................................................ 76
T
ABLE
58:
R
EGISTER
W
ATCHDOG
C
OUNTER
PDI
(0
X
0443).................................................................................................. 76
T
ABLE
59:
SII
EEPROM
I
NTERFACE
R
EGISTER OVERVIEW
................................................................................................... 76
T
ABLE
60:
R
EGISTER
EEPROM
C
ONFIGURATION
(0
X
0500) .................................................................................................. 77
T
ABLE
61:
R
EGISTER
EEPROM
PDI
A
CCESS
S
TATE
(0
X
0501) ............................................................................................. 77
T
ABLE
62:
R
EGISTER
EEPROM
C
ONTROL
/S
TATUS
(0
X
0502:0
X
0503) .................................................................................. 78
T
ABLE
63:
R
EGISTER
EEPROM
A
DDRESS
(0
X
0504:0
X
0507) ................................................................................................ 79
T
ABLE
64:
R
EGISTER
EEPROM
D
ATA
(0
X
0508:0
X
050F
[0
X
0508:0
X
050B]) ...................................................................... 79
T
ABLE
65:
R
EGISTER
EEPROM
D
ATA FOR
EEPROM
E
MULATION
R
ELOAD
(0
X
0508:0
X
050F) ........................................... 80
T
ABLE
66:
MII
M
ANAGEMENT
I
NTERFACE
R
EGISTER
O
VERVIEW
........................................................................................... 80
T
ABLE
67:
R
EGISTER
MII
M
ANAGEMENT
C
ONTROL
/S
TATUS
(0
X
0510:0
X
0511) ................................................................... 82
T
ABLE
68:
R
EGISTER
PHY
A
DDRESS
(0
X
0512) ...................................................................................................................... 83
T
ABLE
69:
R
EGISTER
PHY
R
EGISTER
A
DDRESS
(0
X
0513) ..................................................................................................... 83
T
ABLE
70:
R
EGISTER
PHY
D
ATA
(0
X
0514:0
X
0515) ............................................................................................................. 83
T
ABLE
71:
R
EGISTER
MII
M
ANAGEMENT
ECAT
A
CCESS
S
TATE
(0
X
0516) ........................................................................... 83
T
ABLE
72:
R
EGISTER
MII
M
ANAGEMENT
PDI
A
CCESS
S
TATE
(0
X
0517) .............................................................................. 84
T
ABLE
73:
R
EGISTER
PHY
P
ORT Y
(
PORT NUMBER Y
=0
TO
3)
S
TATUS
(0
X
0518+
Y
) ............................................................ 84
T
ABLE
74:MFCIO
R
EGISTER
C
ONFIGURATION
(0
X
0580+
Y
) .................................................................................................. 85
T
ABLE
75:
FMMU
R
EGISTER OVERVIEW
................................................................................................................................. 86
T
ABLE
76:
R
EGISTER
L
OGICAL
S
TART ADDRESS
FMMU
Y
(0
X
06
Y
0:0
X
06
Y
3) ....................................................................... 86
T
ABLE
77:
R
EGISTER
L
ENGTH
FMMU
Y
(0
X
06
Y
4:0
X
06
Y
5) .................................................................................................... 86
T
ABLE
78:
R
EGISTER
S
TART BIT
FMMU
Y IN LOGICAL ADDRESS SPACE
(0
X
06
Y
6) .............................................................. 86
T
ABLE
79:
R
EGISTER
S
TOP BIT
FMMU
Y IN LOGICAL ADDRESS SPACE
(0
X
06
Y
7) ................................................................ 86
T
ABLE
80:
R
EGISTER
P
HYSICAL
S
TART ADDRESS
FMMU
Y
(0
X
06
Y
8-0
X
06
Y
9) .................................................................... 87
T
ABLE
81:
R
EGISTER
P
HYSICAL
S
TART BIT
FMMU
Y
(0
X
06
Y
A) ........................................................................................... 87
T
ABLE
82:
R
EGISTER
T
YPE
FMMU
Y
(0
X
06
Y
B)...................................................................................................................... 87