Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 6
F IGURE 18 - S HARED SPI BUS CONFIGURATION .................................................................................................................... 42
F IGURE 19 - EEPROM I NTERFACE SIGNALS ........................................................................................................................... 42
F IGURE 20 - R ECOMMENDED LAND PATTERN MEASUREMENTS ................................................................................................. 48
F IGURE 21 - T OP LAYER (1) .................................................................................................................................................... 49
F IGURE 22 - I NNER LAYER (2) ................................................................................................................................................. 49
F IGURE 23 - I NNER LAYER (3) ................................................................................................................................................. 49
F IGURE 24 - I NNER LAYER (4) ................................................................................................................................................. 49
F IGURE 25 - I NNER LAYER (5) ................................................................................................................................................. 49
F IGURE 26 - B OTTOM LAYER (6) ............................................................................................................................................. 49
F IGURE 27 - S OLDERING P ROFILE ........................................................................................................................................... 50
F IGURE 28 - MFCIO BLOCK INTERFACES TO ESC PDRAM ................................................................................................. 111
F IGURE 29 - C ONNECTIONS TO TMC8460 IN E XAMPLE 1 ................................................................................................... 116
F IGURE 30 - C ONNECTIONS TO TMC8460 IN E XAMPLE 2 ................................................................................................... 118
F IGURE 31 - B LOCK STRUCTURE OF THE INCREMENTAL ENCODER UNIT ................................................................................ 121
F IGURE 32 - B LOCK STRUCTURE OF SPI M ASTER U NIT ....................................................................................................... 125
F IGURE 33 - S TEP D IRECTION U NIT B LOCK D IAGRAM ........................................................................................................ 130
F IGURE 34 - S TEP -D IRECTION T IMING ................................................................................................................................. 130
F IGURE 35 - PWM B LOCK D IAGRAM ................................................................................................................................... 134
F IGURE 36 - PWM T IMING ( CENTERED PWM).................................................................................................................... 136
F IGURE 37 - PWM T IMING ( LEFT ALIGNED PWM) ............................................................................................................. 137
F IGURE 38 - PWM T IMING ( RIGHT ALIGNED PWM) .......................................................................................................... 137
F IGURE 39 - C HOPPER M ODES (OFF, L OW S IDE ON, H IGH S IDE ON, L OW S IDE C HOPPER , H IGH S IDE C HOPPER ,
C OMPLEMENTARY L OW S IDE AND HIGH S IDE C HOPPER ) ............................................................................................. 139
F IGURE 40 - C ENTERED PWM WITH PWM#2 SHIFTED FROM C ENTER (E XAMPLE ) ............................................................. 139
F IGURE 41 - B RAKE B EFORE M AKE (BBM) T IMING ( INDIVIDUAL PROGRAMMABLE FOR L OW S IDE AND H IGH S IDE ) ...... 140
F IGURE 6.42 - S TRUCTURE OF THE WATCHDOG UNIT ........................................................................................................... 145
List of Tables
T ABLE 1 : MII INTERFACE SIGNAL DESCRIPTION AND CONNECTION ...................................................................................... 33
T ABLE 2 : PDI SPI INTERFACE SIGNAL DESCRIPTION AND CONNECTION ............................................................................. 35
T ABLE 3 : PDI-SPI COMMANDS .............................................................................................................................................. 35
T ABLE 4 : MFC CTRL SPI INTERFACE SIGNAL DESCRIPTION AND CONNECTION .................................................................. 39
T ABLE 5 : A BSOLUTE M AXIMUM R ATINGS .............................................................................................................................. 44
T ABLE 6 : R ECOMMENDED O PERATING C ONDITIONS .............................................................................................................. 44
T ABLE 7 : TMC8460 POWER CONSUMPTION .......................................................................................................................... 45
T ABLE 8 : P OWER CONSUMPTION BY RAIL .............................................................................................................................. 45
T ABLE 9 : TMC8460 PACKAGE THERMAL BEHAVIOR ............................................................................................................... 45
T ABLE 10 : S OLDERING P ROFILE P ARAMETERS ....................................................................................................................... 50
T ABLE 11 : TMC8460 ADDRESS SPACE ................................................................................................................................... 51
T ABLE 12: R EGISTER T YPE (0 X 0000) ...................................................................................................................................... 56
T ABLE 13: R EGISTER R EVISION (0 X 0001) .............................................................................................................................. 56
T ABLE 14: R EGISTER B UILD (0 X 0002:0 X 0003) ...................................................................................................................... 56
T ABLE 15: R EGISTER FMMU S SUPPORTED (0 X 0004) ............................................................................................................. 56
T ABLE 16: R EGISTER S YNC M ANAGERS SUPPORTED (0 X 0005) ............................................................................................... 56
T ABLE 17: R EGISTER RAM S IZE (0 X 0006) ............................................................................................................................. 56
T ABLE 18: R EGISTER P ORT D ESCRIPTOR (0 X 0007) ............................................................................................................... 57
T ABLE 19: R EGISTER ESC F EATURES SUPPORTED (0 X 0008:0 X 0009) .................................................................................... 57
T ABLE 20: R EGISTER C ONFIGURED S TATION A DDRESS (0 X 0010:0 X 0011) ........................................................................... 58
T ABLE 21: R EGISTER C ONFIGURED S TATION A LIAS (0 X 0012:0 X 0013) ................................................................................ 58
T ABLE 22: R EGISTER W RITE R EGISTER E NABLE (0 X 0020) .................................................................................................... 59
T ABLE 23: R EGISTER W RITE R EGISTER P ROTECTION (0 X 0021) ............................................................................................ 59
T ABLE 24: R EGISTER ESC W RITE E NABLE (0 X 0030) ............................................................................................................. 59
T ABLE 25: R EGISTER ESC W RITE P ROTECTION (0 X 0031) .................................................................................................... 60
T ABLE 26: R EGISTER ESC R ESET ECAT (0 X 0040) ................................................................................................................. 60