Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 5
6.9.2 PWM_CHOPMODE Configuration Register .................................................................................... 138
6.9.3 PWM_ALIGNMENT Configuration Register .................................................................................... 139
6.9.4 POLARITIES Configuration Register ............................................................................................... 139
6.9.5 PWM Value Registers ........................................................................................................................... 140
6.9.6 PULSE_A Configuration Register ...................................................................................................... 140
6.9.7 PULSE_B Configuration Register ...................................................................................................... 140
6.9.8 PULSE_LENGTH Configuration Register .......................................................................................... 140
6.9.9 Asymmetric PWM Configuration Registers .................................................................................. 140
6.9.10 Brake-Before-Make (BBM) ................................................................................................................... 140
6.9.11 BBM_H Configuration Register ......................................................................................................... 140
6.9.12 BBM_L Configuration Registers ........................................................................................................ 140
6.9.13 Emergency Switch Input Off-State ................................................................................................. 141
6.10 MFCIO G ENERAL P URPOSE IO U NIT .................................................................................................................. 142
6.10.1 GPIO Registers ....................................................................................................................................... 142
6.10.2 General purpose Inputs (GPI) .......................................................................................................... 142
6.10.3 General purpose Outputs (GPO) ...................................................................................................... 142
6.10.4 Emergency Switch Input State ........................................................................................................ 142
6.11 MFCIO W ATCHDOG U NIT ................................................................................................................................... 143
6.11.1 General Function ................................................................................................................................... 143
6.11.2 Watchdog Register Set ....................................................................................................................... 143
6.12 MFCIO IRQ U NIT AND R EGISTER S ET ............................................................................................................... 147
2.1.6 IRQ_CFG Register .................................................................................................................................. 147
2.1.7 IRQ_FLAGS Register .............................................................................................................................. 147
6.13 MFCIO E MERGENCY S WITCH I NPUT ................................................................................................................... 148
6.13.1 Activation & Usage ............................................................................................................................... 148
6.13.2 Re-Activation ........................................................................................................................................... 148
6.14 A UXILIARY C LOCK O UTPUT .................................................................................................................................. 148
6.15 AL-S TATE O VERRIDE C ONFIGURATION ................................................................................................................ 149
7 ESD SENSITIVE DEVICE ......................................................................................................................................... 150
8 DISCLAIMER .............................................................................................................................................................. 150
9 REVISION HISTORY ................................................................................................................................................ 151
List of Figures
F IGURE 1 - TMCL-IDE WITH DIRECT REGISTER ACCESS TO THE TMC8460-BI ON ITS EVALUATION BOARD ..................... 15
F IGURE 2 - W IZARD S TART S CREEN ....................................................................................................................................... 16
F IGURE 3 - W IZARD D EVICE S ELECTION AND F EATURE S ELECTION ....................................................................................... 17
F IGURE 4 - W IZARD R EGISTER S ELECTION AND C ONFIGURATION V IEW .............................................................................. 18
F IGURE 5 - W IZARD OUTPUT VIEW WITH EEPROM CONFIGURATION STRING AND FIRMWARE C- CODE SNIPPETS ............ 19
F IGURE 6 - A PPLICATION DIAGRAM USING ONLY THE LOCAL APPLICATION CONTROLLER TO INTERFACE THE APPLICATION 20
F IGURE 7 - A PPLICATION DIAGRAM USING THE MFCIO BLOCK FEATURES TO REDUCE SOFTWARE OVERHEAD AND PROVIDE
REAL - TIME HARDWARE SUPPORT TO THE MCU. O THER APPLICATION PARTS MAY STILL BE CONNECTED TO THE MCU.
......................................................................................................................................................................................... 21
F IGURE 8 - A PPLICATION DIAGRAM WITHOUT MCU. T HE TMC8460 IS USED IN DEVICE EMULATION MODE . SPI SLAVE
CHIPS AND OTHER APPLICATION PERIPHERALS CAN BE CONNECTED TO THE MFCIO BLOCK . T HE E THER CAT MASTER
CAN DIRECTLY CONTROL ALL THE APPLICATION FUNCTIONS . ......................................................................................... 21
F IGURE 9 : MII I NTERFACE S IGNALS ...................................................................................................................................... 33
F IGURE 10 - PDI SPI I NTERFACE S IGNALS ........................................................................................................................... 35
F IGURE 11 - 2 BYTE ADDRESSING MODE ................................................................................................................................. 36
F IGURE 12 - 3 BYTE ADDRESSING MODE ................................................................................................................................. 36
F IGURE 13 - PDI SPI TIMING EXAMPLE ................................................................................................................................. 38
F IGURE 14 - MFC CTRL SPI INTERFACE SIGNALS ................................................................................................................. 39
F IGURE 15 - 2- BYTE MFC REGISTER ACCESS ........................................................................................................................... 40
F IGURE 16 - 3- BYTE MFC REGISTER ACCESS ........................................................................................................................... 40
F IGURE 17 - MFC C ONTROL SPI TIMING EXAMPLE ................................................................................................................ 41