Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 48
3.12 Layout Considerations
The required board area for the TMC8460, EEPROM, PHYs, capacitors and LEDs is below 12.5cm
2
on a six-
layer board.
For best soldering results, only the BGA pads should be exposed under the TMC8460, while vias, traces
and ground/power planes should be covered by the soldermask. It is not necessary to use blind or
buried vias. Use the following guideline for routing to regular vias from the BGA pads. Traces from pads
on the outermost rows can also be routed directly on the top layer.
Pad dia.
0.3mm
Mask hole dia.
0.45mm
Tra
ce
w
i
dth
0.15mm
P
a
d to
v
ia
dist
a
nce
0.56
m
m
Via hole dia.
0.25mm
Restring dia.
0.5mm
Pad distance
0.8mm
Pad distance
0.8mm
Figure 20 - Recommended land pattern measurements
The routing of the traces to the two PHYs should be as short as possible since these signals are timing
critical. Since the pads of the MII signals are all on one side of the TMC8460, most of the signals can
be routed only on the top layer without the need for vias.
It is sufficient to treat other traces like SPI or all MFC signals in groups (e.g. the PDI_SPI signals or the
PWM outputs), where the variance in trace length is small for all signals of the same group.