Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 39
3.6 MFC CTRL SPI
The MFC Control SPI is a SPI mode 3 slave with low active chip select. It allows an external
microcontroller to access the MFC registers. The SPI clock frequency can be up to 30MHz.
The following diagram shows all signals related to the MFC CTRL SPI interface.
MFC_CTR_SPI_SCK
TMC8460
MFC_CTRL_SPI_CSN
MFC_CTRL_SPI_MOSI
MFC_CTRL_SPI_MISO
MFCIO_IRQ
PDI_SHARED_SPI_BUS
Figure 14 - MFC CTRL SPI interface signals
Table 4 : MFC CTRL SPI interface signal description and connection
TMC8460 pin Usage/description Typical µC pin name
MFC_CTRL_SPI_SCK SPI master clock SCK
MFC_CTRL_SPI_CSN SPI chip select for the TMC8460 SSx
MFC_CTRL_SPI_MOSI Master out slave in data MOSI
MFC_CTRL_SPI_MISO Master in slave out data MISO
MFCIO_IRQ Configurable IRQ from MFCIO block General purpose IO
PDI_SHARED_SPI_BUS 0: separate SPI buses for PDI and MFC CTRL
1: shared/common SPI bus for PDI and MFC CTRL
with 2 CSN signals using the PDI SPI bus. The SPI
bus signals MFC_CTRL_SPI_SCK,
MFC_CTRL_SPI_MISO, MFC_CTRL_SPI_MOSI can be
left open in this case
General purpose IO or
connected to either
ground or 3.3V.
The protocol of the MFC CTRL SPI is the same as the PDI SPI interface. The addresses for register access
are calculated using the register number (from 0 to 44) and the byte number in each register. To
calculate the address, the register number is shifted left by 4 bits and the byte number is added as the
4 lowest bits.
Access using the 3 byte addressing mode is possible, and can be used when 2 byte mode is not
implemented for the PDI SPI but since the highest bits of the address are always 0, accessing the MFC
Control SPI via 2 byte mode is sufficient.