Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)

MIIx_RXDV Receive data valid RX_DV

MIIx_RXER Receive error RX_ER

MIIx_TXEN Transmit enable TX_EN

MIIx_TXCLK Transmit clock (optional for automatic TX shift) TX_CLK

MIIx_TXD[3:0] Transmit data TXD3…TXD0

MCLK Management Interface clock,

MCLK is driven rail-to-rail, idle value is High.

MDC

MDIO Management Interface data,

MDIO must have a pull-up resistor (4.7 kΩ

recommended)

MDIO

3.4.2 PHY Configuration Pins

Besides the standard MII and MI interface signals, the TMC8460 has three configuration pins related to

the PHYs.

• LINK_POLARITY: this pin allows configuring the polarity of the link signal of the PHY. PHYs of

different manufacturers may use different polarities at the PHY’s pins. In addition, some PHYs allow

for bootstrap configuration with pull-up and pull-down resistors. This bootstrap information is used

by the PHY at power-up / reset and also influences the polarity of the original pin function.

Therefore, the link polarity needs to be configurable.

• PHY_OFFSET: The TMC8460 addresses Ethernet PHYs using logical port number plus PHY address

offset. Typically, the Ethernet PHY addresses should correspond with the logical port number, so

PHY addresses 0 to 1 are used. A PHY address offset of 1 can be applied (PHY_OFFSET = ‘1’) which

moves the PHY addresses to a range of 1 to 2. The TMC8460 expects logical port 0 to have PHY

address 0 plus PHY address offset.

• MIIx_TX_SHIFT[1:0]: TMC8460 and Ethernet PHYs share the same clock source. Thus, TX_CLK from

the PHY has a fixed phase relation to the MII interface TX part of TMC8460. Thus, TX_CLK must not

be connected and the delay of a TX FIFO inside the IP Core is saved.

In order to fulfill the setup/hold requirements of the PHY, the phase shift between TX_CLK and

MIIx_TX_EN and MIIx_TXD[3:0] has to be controlled.

o Manual TX Shift compensation with additional delays for MIIx_TXEN/MIIx_TXD[3:0] of 10, 20,

or 30 ns. Such delays can be added using the TX Shift feature and applying

MIIx_TX_SHIFT[1:0]. MIIx_TXH_SHIFT[1:0] determine the delay in multiples of 10 ns for each

port. Set MIIx_TXCLK to zero if manual TX Shift compensation is used.

o Automatic TX Shift compensation if the TX Shift feature is selected: connect MIIx_TXCLK and

the automatic TX Shift compensation will determine correct shift settings. Set

MIIx_TX_SHIFT[1:0] to 0 in this case.

3.5 PDI SPI

The PDI SPI interface is the interface used to access the ESC registers and the process data RAM from

an external microcontroller. The SPI clock frequency can be up to 30 MHz.

The interface is configurable via the EEPROM. The default configuration (SPI mode 3, low active chip

select) is recommended. For further details, see the ESC SPI slave configuration registers in Section 5.28.

The following diagram shows all signals related to the PDI SPI interface.