Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)

3.4 Ethernet PHYs

The TMC8460-BI requires Ethernet PHYs with MII interface.

The MII interface of the TMC8460 is optimized for low additional delays by omitting a transmit FIFO.

Therefore, additional requirements to Ethernet PHYs exist and not every Ethernet PHY is suited.

Therefore, please see the Ethernet PHY Selection Guide provided by the ETG:

http://download.beckhoff.com/download/Document/EtherCAT/Development_products/AN_PHY_Selection_

GuideV2.3.pdf.

The TMC8460-BI has been successfully tested in combination with the following Ethernet PHYs so far:

• IC+ IP101GA: http://www.icplus.com.tw/pp-IP101G.html

• Micrel KSZ8721BLI: http://www.micrel.com/_PDF/Ethernet/datasheets/ks8721bl-sl.pdf

• Micrel KSZ8081: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ8081MNX-RNB.pdf

The clock source of the PHYs is the same as for the TMC8460-BI (25 MHz).

3.4.1 Ethernet PHY MII interface and MI interface

100-Mbit Ethernet PHYs with MII interface are required. In addition, they need to provide a link signal

indicating stable 100Mbit bus connection.

The following diagram shows the interface pins. The table in Section 3.3 contains the pin descriptions

of the interface. TX_CLK is optional. It is used for automatic TX Shift compensation.

MIIx_LINK

TMC8460

MIIx_RXCLK

MIIx_RXD[3:0]

MIIx_RXDV

MIIx_RXER

MIIx_TXEN

MIIx_TXCLK

MIIx_TXD[3:0]

MCLK

MIIx_TX_SHIFT[1:0]

PHY_OFFSET

MDIO

LINK_POLARITY

Figure 9 : MII Interface Signals

Table 1 : MII interface signal description and connection

TMC8460 pin Usage/description Typical PHY pin name

MIIx_LINK Input signal provided by the PHY if a stable 100

Mbit/s (Full Duplex) link is established.

MIIx_LINK must be constantly driven with the

configured polarity during operation.

PHY and configuration

dependent, typically

one of the status LED

pins

MIIx_RXCLK Receive clock RX_CLK

MIIx_RXD[3:0] Receive data RXD3…RXD0