Datasheet

ManualsBrandsTrinamic ManualsDevelopment Boards & KitsStepper Driver Evaluation Board ... SPI/STEP / DIR

TMC8460-BI Datasheet (V100 / 2016-Sep-01)

G19

MII1_RXD[1] I MII interface to PHY of link in port

F20

MII1_RXD[2] I MII interface to PHY of link in port

F19

MII1_RXD[3] I MII interface to PHY of link in port

H20

MII1_RXDV I MII interface to PHY of link in port

J19

MII1_RXER I MII interface to PHY of link in port

J18

MII1_TX_SHIFT[0] I

Used for clock shift compensation on TX port, Weak

internal pull down

G18

MII1_TX_SHIFT[1] I

Used for clock shift compensation on TX port, Weak

internal pull down

D20

MII1_TXCLK I MII interface to PHY of link in port

C20

MII1_TXD[0] O MII interface to PHY of link in port

C19

MII1_TXD[1] O MII interface to PHY of link in port

B19

MII1_TXD[2] O MII interface to PHY of link in port

A20

MII1_TXD[3] O MII interface to PHY of link in port

A19

MII1_TXEN O MII interface to PHY of link in port

T18

MII2_LINK I MII interface to PHY of link out port

P20

MII2_RXCLK I MII interface to PHY of link out port

U19

MII2_RXD[0] I MII interface to PHY of link out port

T20

MII2_RXD[1] I MII interface to PHY of link out port

T19

MII2_RXD[2] I MII interface to PHY of link out port

R20

MII2_RXD[3] I MII interface to PHY of link out port

V19

MII2_RXDV I MII interface to PHY of link out port

V20

MII2_RXER I MII interface to PHY of link out port

R18

MII2_TX_SHIFT[0] I

Used for clock shift compensation on TX port, weak

internal pull down

P18

MII2_TX_SHIFT[1] I

Used for clock shift compensation on TX port, Weak

internal pull down

N20

MII2_TXCLK I MII interface to PHY of link out port

N19

MII2_TXD[0] O MII interface to PHY of link out port

M19

MII2_TXD[1] O MII interface to PHY of link out port

L20

MII2_TXD[2] O MII interface to PHY of link out port

L19

MII2_TXD[3] O MII interface to PHY of link out port

J20

MII2_TXEN O MII interface to PHY of link out port

P15

PHY_OFFSET I PHY Address Offset: 0 = Offset = 0, 1 = Offset = 1

E18

MCLK O

PHY management clock,

connect all PHYs to this bus

F18

MDIO I/O

PHY management data,

connect all PHYs to this bus if required,