Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 27
L15
MFC_GPIO[2] I/O MFCIO block GPIO port, configurable
M15
MFC_GPIO[3] I/O MFCIO block GPIO port, configurable
N15
MFC_GPIO[4] I/O MFCIO block GPIO port, configurable
K16
MFC_GPIO[5] I/O MFCIO block GPIO port, configurable
L16
MFC_GPIO[6] I/O MFCIO block GPIO port, configurable
M16
MFC_GPIO[7] I/O MFCIO block GPIO port, configurable
Y16
MFC_PWM_HS_0 O MFCIO block PWM unit high side output
Y15
MFC_PWM_HS_1 O MFCIO block PWM unit high side output
W13
MFC_PWM_HS_2 O MFCIO block PWM unit high side output
W15
MFC_PWM_LS_0 O MFCIO block PWM unit low side output
W14
MFC_PWM_LS_1 O MFCIO block PWM unit low side output
Y13
MFC_PWM_LS_2 O MFCIO block PWM unit low side output
V14
MFC_nES I
low active (not) Emergency Stop/Switch/Halt (to bring
PWM or other outputs into a safe state), the event
must be cleared actively, has weak internal pull down,
must be driven high for normal operation
U13
MFC_PWM_PULSE_A O
PWM Trigger Pulse for e.g. ADC synchronization,
MFC_PWM_PULSE_A is configurable and high for one
clock cycle in each PWM cycle
U18
MFC_PWM_PULSE_AB O
PWM Trigger Pulse for e.
g. ADC synchronization,
MFC_PWM_PULSE_AB combines MFC_PWM_PULSE_A and
MFC_PWM_PULSE_B in one signal
U11
MFC_PWM_PULSE_B O
PWM Trigger Pulse for e.g. ADC synchronization,
MFC_PWM_PULSE_B is configurable and high for one
clock cycle in each PWM cycle
W10
MFC_PWM_PULSE_C O
PWM Trigger Pulse for e.g. ADC synchronization,
MFC_PWM_PULSE_C is high for one clock cycle in the
center of each PWM cycle
Y10
MFC_PWM_PULSE_S O
PWM Trigger Pulse for e.g. ADC synchronization,
MFC_PWM_PULSE_S is high for one clock cycle on each
PWM cycle start
R13
MFC_SD_DIR O MFCIO block Step/Direction unit output
T13
MFC_SD_STP O MFCIO block Step/Direction unit output
F16
MFC_SPI_CS0 O MFCIO block SPI master unit interface
G17
MFC_SPI_CS1 O MFCIO block SPI master unit interface
G16
MFC_SPI_CS2 O MFCIO block SPI master unit interface
H17
MFC_SPI_CS3 O MFCIO block SPI master unit interface
E16
MFC_SPI_MISO I MFCIO block SPI master unit interface
E17
MFC_SPI_MOSI O MFCIO block SPI master unit interface
M17
MFC_SPI_SCK O MFCIO block SPI master unit interface
H16
LINK_POLARITY I
selects polarity of the PHYs link signal:
0 = low active, 1 = high active
K18
MII1_LINK I MII interface to PHY of link in port
E20
MII1_RXCLK I MII interface to PHY of link in port
H19
MII1_RXD[0] I MII interface to PHY of link in port