Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)

LATCH_IN0, LATCH_IN1, SYNC_OUT0, SYNC_OUT1, NRST_OUT, EN_16MHZ_OUT and CLK_16MHZ_OUT are

optional signals that can be used depending on the specific use case.

Configuration Pins with their setting in this example:

LINK_POLARITY 1 (+3.3V) MII_LINK signal from PHYs is high active

PHY_OFFSET 0 (GND) PHY address offset is 0

PROM_SIZE 1 (+3.3V) EEPROM is 32kbit or larger (4Mbit max.)

RESET_OUT_POLARITY 0 (GND) The RESET_OUT signal is low active

External resistors are required on the MDIO line and for four (4) of the reserved pads.

3.2.4 MII 1 (EtherCAT Input)

These are the connections to the first PHY, representing the input port of the EtherCAT device.

3.2.5 MII 2 (EtherCAT Output)

These are the connections to the second PHY, representing the output port of the EtherCAT device.