Datasheet

TMC8460-BI Datasheet (V100 / 2016-Sep-01)

3.2 Samples Circuits

3.2.1 IC supply

Only a minimal amount of decoupling capacitors is shown here.

If possible every supply pin (1.2V and 3.3V) should have a separate 100nF capacitor connected between

it and GND as close to the pin as possible.

Larger capacitor values can be used on the 3.3V and 1.2V supply rails for increased stability.

3.2.2 PDI interface

This is the default configuration for the PDI SPI interface; both PDI_EMULATION and

PDI_SHARED_SPI_BUS are tied to GND.

PDI__EMULATION = 0 means that the processor connected to the PDI SPI pins has full control over the

ESC registers, the memory and the EtherCAT state machine.

PDI_SHARED_SPI_BUS = 0 means that the signals of the PDI SPI and MFC CTRL SPI buses are

completely separate.

The processor can also use the extra signals for Start-/End-Of-Frame and the PDI Watchdog.

3.2.3 Miscellaneous signals

CLK_25MHZ is the clock input, which should be the same signal as the clock for both PHYs. The traces

from the oscillator to the TMC8460 and the PHYs should have approximately the same length to avoid

timing problems.