Datasheet

TMC8460-BI Datasheet (V1.00 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 147
6.12 MFCIO IRQ Unit and Register Set
The MFCIO block of the TMC8460 provides a dedicated IRQ output signal to a local microcontroller to
indicate certain events and conditions.
The pin MFCIO_IRQ can be configured and read out using the two registers shown in the next table.
Table 154 : MFCIO IRQ unit registers
MFCIO
direct
access
register
address
#
Register
Name
R/W
Size
[bit]
Description
36 IRQ_CFG W 16
Masking / Enabling of the required IRQ sources
which are or-ed to set the MFCIO_IRQ output
signal
Bit 0 : Encoder unit N-event
Bit 1 : Step/Direction unit target reached signal
Bit 2 : SPI unit new data available
Bit 3 : Watchdog unit timeout
Bit 4 : PWM Unit PWM cycle start trigger
Bit 5 : PWM Unit PWM cycle center trigger
Bit 6 : PWM Unit configurable pulse A
Bit 7 : PWM Unit configurable pulse B
Bits 14..8 : reserved, unused
Bit 15 : activation of external low active emergency
switch signal MFC_nES
37 IRQ_FLAGS R 16
Status register to read the IRQ flags of the masked
IRQ sources
2.1.6 IRQ_CFG Register
The IRQ mask register allows to enable/disable certain IRQ trigger events of the MFCIO block.
This is useful when MFCIO sub blocks are used at the same time or are not needed.
A special option is to enable the MFC_nES emergency switch input signal. Setting the mask bit here in
the IRQ_CFG register has two effects:
a) It functionally enables this pin. Now all functional outputs of the TMC8460 are affected if
MFC_nES goes low.
b) It masks the MFC_nES event (falling edge) as IRQ source to the MFCIO_IRQ output.
In case of an event on the MFC_nES input, the respective flag in the IRQ_FLAGS[15] register can only be
unset be either doing a device reset or by actively writing 2 times into the IRQ_CFG register at bit
position 15. Thereby, the existing IRQ mask at bit 15 must first be set to zero and then set back to 1
again. This way, the internal emergency flag is unset.
2.1.7 IRQ_FLAGS Register
This register can be read out after the IRQ was set to identify the IRQ source, especially when more
than one IRQ source was enabled.
Each flags corresponds to the same IRQ source bit position as in IRQ_CFG register.
Reading this registers clears all individual IRQ source bits except the MFC_nES flag bit at position 15.