Datasheet

TMC8460-BI Datasheet (V1.00 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 143
6.11 MFCIO Watchdog Unit
6.11.1 General Function
The watchdog timer allows monitoring of external signals, or monitoring of ETHERCAT activity. A certain
condition can be chosen for retriggering the watchdog, i.e. a certain input signal constellation. In case
this constellation does not occur at least once within a pre-programmable time period, the watchdog
timer will expire and will trigger a certain watchdog action. To avoid static reset of the watchdog, the
watchdog input condition is edge sensitive, i.e. it becomes reset when the condition goes active
respectively goes inactive. Once the watchdog expires, the watchdog safety circuitry becomes active.
This action can bring I/O lines into a certain state, in order to allow the system to return to a known,
safe condition. Therefore, all I/O lines are directly mapped to the GPIO ports of the chip, so that they
perform independently of the actually configured peripheral configuration. The watchdog action can be
chosen to remain active continuously, until it becomes reset by a watchdog re-configuration, or it can
be programmed to return to normal operation state, once the selected condition becomes true again.
In an optional use case, the watchdog timer can be used to measure the maximum delay in between
of the occurrence of certain input conditions, in between of SPI frames, etc.
6.11.2 Watchdog Register Set
Once initialized, the watchdog timer monitors the application for activity and allows setting of pre-
programmed I/O patterns, in case the time limit is expired without activity. In order to allow tuning of
this time limit, the maximum time between two trigger events becomes measured. This function also
allows delay time measurement for input channels (i.e. when no watchdog action is chosen). The
watchdog timeout counter starts from zero up to WD_TIME. When it reaches WD_TIME, it triggers the
watchdog action.
The selected watchdog event resets the timeout counter. As trigger sources, the internal ETHERCAT start
of frame, the two SPI chip select signals as well as any combination of I/O lines can be used. For the
I/O lines, the polarity and edge are programmable. When using a GPIO programmed to output as
watchdog trigger, the watchdog circuitry will monitor the real output by checking the polarity of the
output signal. This way, also a short circuit condition will be detected. The chip select signals respond
to a rising edge (i.e. when the SPI interface loads the SPI shift register data into the corresponding
registers).
Table 151 : MFCIO watchdog unit registers
MFCIO
direct
access
register
address
#
Register
Name
R/W
Size
[bit]
Description
38 WD_TIME W/R 32
Watchdog time 32 bit, unsigned
0 = Watchdog off
Time = Number of 25MHz clocks
39 WD_CFG W/R 8
Bit 0
cfg_persistent
0 The watchdog action ends when the next
trigger event occurs
1 A timeout situation can only be cleared by
rewriting WD_TIME
Bit 1
cfg_pdi_csn_enable
1 Retrigger by positive edge on PDI_SPI_CSN
Bit 2
cfg_mfc_csn_enable
1 Retrigger by positive edge on
MFC_CTRL_SPI_CSN