Datasheet

TMC8460-BI Datasheet (V1.00 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 133
6.8.2 Step Counter
The step counter counts the number of steps, taking the direction into account. This is a read only
register. For initialization to zero a configuration bit within the step direction configuration register hast
to be written.
6.8.3 Step Target
The step target defines the number of steps to be made for the step mode until stop. This register can
be overwritten at any time. When the number of steps has been made, the unit stops outputting S/D
pulses. When read, it gives the remaining numbers that must still be made.
6.8.4 Step Length
The duration of the step pulse – the step length (SL) - signal is programmable for adaption to external
power stages.
M AXIMUM S TEP L ENGTH
The step pulse length t
STEP_PULSE
[s] must be lower than the time t
STEP
[s] between step pulses to have step
pulses. The condition t
STEP_PULSE
[s] < t
STEP
[s] must be ensured by the application.
6.8.5 Step-to-Direction Delay
The delay between the first step pulse after a change of the direction is programmable for adaption to
external power stages to take external delay paths into account.
6.8.6 Step Direction Unit Configuration
The step direction configuration defines the mode of operation (continuous or finite number of step
pulses), polarity of step pulse signal and direction signal. One bit is for zeroing of step pulse counter.
On bit is for enabling and disabling of the step pulse unit.
6.8.7 Interrupt Output Signal
A signal IRQ_TAR_REACHED of a single clock pulse length indicated indicates that a TARGET position is
reached in terms of step counts.