Datasheet

TMC8460-BI Datasheet (V1.00 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 132
Table 145 : MFCIO S/D Unit real world unit relations
Parameter Value Description / Function Comment
f
CLK
[Hz] 25 MHz clock frequency of step direction unit clock frequency of the
step direction unit
t
CLK
[s] 40 ns clock period length t
CLK
[s] = 1 / f
CLK
[Hz]
f
STEP
[Hz]
f
STEP
[Hz] = (f
CLK
[Hz]/2^32)*(SD_CH#_SR)
step frequency,
programmed via step rate
accumulation constant
SD_CH#_SR
Max. f
STEP
[Hz] 12.5
MHz
Theoretical maximum value
for fStep. Usable step
frequency depends on step
pulse length configuration.
t
STEP
[s] t
STEP
= 1 / f
STEP
[Hz] time between steps
t
STEP_PULSE
[s] t
STEP_PULSE
[s] = (STP_LEN_I+1) / f
CLK
[Hz] step pulse length must be
lower than time between
step pulses!
t
STEP_PULSE
[s] < t
STEP
[s]
DIR DIR = 0  positive direction,
DIR = 1  negative direction,
direction is depending on sign of step rate
register SD_CH#_SR where the step rate
register is 2th complement
direction signal, depending
of step rate (SR) parameter,
DIR = 0 if SR > 0 or SR = 0,
DIR = 1 if SR < 0
t
STEP1st
[s]
time to 1st step pulse since WR=0 with
t
STEP1st
[s] = 2^32 / STP_RT_I * t
CLK
[s]
+ ( STP_DLY_I + 1 )
* t
CLK
[s] + ( 2 * t
CLK
[s] );
Time between write until
the first step pulse occurs
t
STEP1stWR
[s]
time to 1st step pulse since WR=0 step
delay plus 1 internal clock plus 2 clock
cycles to pulse length
Internal processing adds
an delay
SD_CH_SR
Writing SD_CH_SR = 0 clears the step
accu register step_accu_ff and stops
step pulse generation.
6.8.1 Step Direction Accumulation Constant
The step direction accumulation constant determines the time t
STEP
between two successive step pulses
– the step rate (SR). Each internal PWM clock accumulates an accumulator according to a = a + c with
the accumulator constant c. Toggle of the MSB of the accumulator register a triggers a step pulse. With
this principle, the step frequency is smarter adjustable compared to a simple frequency divider. Writing
c = 0 clears the accumulator and stops the step pulse generation. The step pulse frequency f
STEP
[Hz] = (
f
CLK
[Hz] / 2^32 ) * c. To calculate the accumulation c one just have to calculate
c = int( 2^32 * ( f
CLK
[Hz] / f
STEP
[Hz] ) ) = int ( 4294967296 * ( f
CLK
[Hz] / f
STEP
[Hz] )
T IME TO F IRST S TEP
Due to internal processing, the time to the first step since write register write is
t
STEP1st
[s] = 2^32 / SD_SR * t
CLK
[s] + (STP_SDY_I + 1 ) * t
CLK
[s] + ( 2 * t
CLK
[s] )