Datasheet

TMC8460-BI Datasheet (V1.00 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 127
Bit 3 can be used for datagrams longer than 64 bit. With this bit set, the chip select line is held low
after the transmission, allowing more transmissions in the same datagram. Before the last transmission,
this bit must be set to 0 again so that the chip select line goes high afterwards, ending the datagram.
Bits 1 and 0 define which chip select line (which slave) is used for the next transmission.
6.7.6 SPI_STATUS
Bit 0 of this register is the Ready indicator for the SPI master unit. When this bit is set, a new transfer
can be started. When this bit is 0 and the start of a new transfer is triggered, the trigger is ignored, the
currently active transfer is finished but the new transfer is not started.
6.7.7 SPI_LENGTH
This register defines the SPI datagram length in bits. Any length from 1 to 64 bits is possible.
SPI datagram length = SPI_LENGTH+1
6.7.8 SPI_TIME
This register defines the bit length and thus the SPI clock frequency.
The duration of one SPI clock cycle can be calculated as t_SCK = (4+(2*SPI_TIME))/25MHz, the SPI clock
frequency is f_SCK = 25MHz/(4+(2*SPI_TIME)).
The delay between the falling edge of CSN (becoming active) and the first SCK edge and the last SCK
edge and the rising edge of CSN is always a half SCK clock cycle (t_SCK/2).
6.7.9 SPI Examples
TMC262 ON SPI CHANNEL 0
This example shows the configuration of the SPI master unit for a TMC262 as SPI slave 0 and the
transfer of data to the TMC262’s DRVCONF register.
Use 3.125 MHz SPI clock (25MHz/(4+(2*2))) = (25MHz/8)
SPI_TIME <= 0x02
Use 20 bit datagrams
SPI_LENGTH <= 0x13
Start on TX write, SPI-Mode 3, MSB first, single datagrams, Slave 0)
SPI_CONF <= 0x0060
Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
Write Data into TX register (e.g. TMC262 DRVCONF register, all 64bit are shown)
SPI_TX_DATA <= 0x00000000000EF010
Wait until SPI-Master is ready
while (SPI_STATUS & 0x01 != 0x01)
Read Data from RX register
rxdatagram = SPI_RX_DATA
C HAIN OF 10 74 XX 595 SHIFT REGISTERS USED AS DIGITAL 80 OUTPUTS ( GOOD EXAMPLE )
This example shows the transmission of a longer datagram, in this case 80 bits that are shifted into a
chain of 74xx595 shift registers. The NCS of the SPI interface can be used as the storage clock of the
74xx595 to transfer the contents of the shift register into the storage register. The data that should be
sent is 0x5555AAAA5555AAAA55AA.
It is recommended to split the data into two chunks of 40 bits each: 0x5555AAAA55 and 0x55AAAA55AA.
Configuration and first transmission
Use 6.25 MHz SPI clock (25MHz/(4+(2*0))) = (25MHz/4)
SPI_TIME <= 0x00
Use a 40 bit datagram