Datasheet

TMC8460-BI Datasheet (V1.00 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 126
000: Start when data is written into TX
register
001: Start on beginning of PWM cycle
010: Start on center of PWM cycle
011: Start on PWM A mark
100: Start on PWM B mark
101: Start on PWM A&B marks
111: Start on single trigger (Bit 15)
Bit 6: SPI clock polarity
Bit 5: SPI clock phase
Bit 4: LSB first
Bit 3: Keep CS low after transfer for transfers
over 64bit
Bits 1..0: Selection of SPI slave
9 SPI_STATUS R 8
Bit 0: ready-indicator, if set a new transmission can be
started
Bits 7:1: unused
10 SPI_LENGTH W 8
Bits 5..0: SPI datagram length = SPI_LENGTH+1
Bits 7..6: unused
11 SPI_TIME W 8 Defines bit length and thereby the SPI frequency
6.7.3 SPI_RX_DATA
For SPI transfers with less than 64 bit, the upper bits of this register are unused.
6.7.4 SPI_TX_DATA
For SPI transfers with less than 64 bit, the upper bits of this register are unused.
Unless configured differently in SPI_CONF Bits 10..8, writing to this register starts the SPI transfer.
6.7.5 SPI_CONF
Bits 10..8 allow a configuration when the data transmission should start, they are interpreted as a 3 bit
number:
- In the reset configuration 0, the transmission always starts when data is written to the SPI_TX
register.
- The settings 1 to 5 link the start of the transmission to the PWM unit, allowing synchronization
between the PWM cycle and for example a SPI ADC for current measurement. The trigger sources
are the five PWM_PULSE signals that are also available as external signals. Please refer to Section
6.9 for details about these pulses.
- Setting 7 is a single shot trigger that starts only one transmission when Bit 15 is written to 1.
Bit 6 and 5 define the clock polarity and phase of the SPI signals which define what the idle state of
the SCK signal is and when output data is changed and when input data is sampled.
Table 142 : MFCIO SPI master unit SPI mode configuration
Clock
polarity
Clock
phase
SPI
mode
MOSI
change
MISO
sample
0 0 0 SCK falling edge SCK rising edge
0 1 1 SCK rising edge SCK falling edge
1 0 2 SCK rising edge SCK falling edge
1 1 3 SCK falling edge SCK rising edge
Bit 4 reverses the bit order in the transmission, the least significant bit of SPI_TX_DATA (Bit 0) is
transmitted first, the least significant bit of SPI_RX_DATA is the first received bit, the most significant
bit of SPI_TX_DATA is transmitted last and the most significant bit of SPI_RX_DATA is the last bit received.