Datasheet

TMC8460-BI Datasheet (V1.00 / 2016-Sep-01)

6.7 MFCIO SPI Master Unit

The SPI Master Unit provides an interface for up to four SPI slaves with a theoretically unlimited

datagram length using multiple accesses.

Figure 32 - Block structure of SPI Master Unit

The basic configuration requires setting the SPI frequency/bit length, the datagram length and the SPI

mode (clock polarity and phase). Extended settings are a special start-of-transmission trigger linked to

the PWM unit, the bit order, selection of one of the four SPI slaves and datagram length extension.

6.7.1 SPI Master Unit Signals

Table 140 : MFCIO master unit signals

Signal I/O Function

SPI_CS0…SPI_CS3 Out Chip select lines 0..3

SPI_SCK Out SPI clock output

SPI_MOSI Out SPI data output (Master Out Slave In)

SPI_MISO In SPI data input (Master In Slave Out)

6.7.2 SPI Master Unit Register Set

Table 141 : MFCIO SPI master unit register set

MFCIO

direct

access

address #

Size

[bit]

Description

6 SPI_RX_DATA R 64 Received data from last SPI transfer

7 SPI_TX_DATA W 64 Data to transmit on next SPI transfer

8 SPI_CONF W 16

SPI Master configuration and control

Bit 15: Start transfer once when this bit is set

and trigger

config is set to 7

Bits 10..8: Trigger config for transmission start

values