Datasheet

TMC8460-BI Datasheet (V1.00 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 122
Bit 7: neg_edge N event is generated when N input
becomes inactive
Bit 6: pos_edge N event is generated when N input
becomes active
Bit 5: clr_once N event is generated only once
when all conditions are met
Bit 4: clr_cont N event is generated every time
all conditions are met
Bit 3: ignore_AB N event is generated regardless of A and
B signals
Bit 2: pol_N Active polarity for N input
Bit 1: pol_B Required B input polarity for N event
Bit 0: pol_A Required B input polarity for N event
1 ENC_STATUS R 8
Status flag showing that N event was generated
Bit 0: Status bit
2 X_ENC (W) W 32 Register to set a new encoder position
3 X_ENC (R) R 32 Encoder position
4 ENC_CONST W 32 Encoder constant in 16 bit integer and 16 bit fractional part
5 ENC_LATCH R 32 Latched encoder position
6.6.3 ENC_MODE
clear_status (Bit 15)
The status flag is not cleared by reading ENC_STATUS but needs to be reset by writing this bit to 1.
enc_sel_decimal (Bit 10)
With this bit set to 0, the encoder constant is interpreted as a fixed point binary number with the lower
16 bits representing the fractional part.
Whis this bit set to 1, the lower 16 bits of the encoder constant represent 1/10000th step. The range
for the fractional part in this case is 0 <= x <= 9999 and should not be set higher. A fractional part of
10000 equals an additional integer part of 1.
clr_enc_x (Bit 8)
If this bit is set to 1, the encoder counter (ENC_X) is reset to 0 in case of an N event.
Regardless of this bit, the value of the encoder counter is always transferred to the ENC_LATCH register
at an N event.
The N event is generated when some configurable conditions are met:
- If the N input matches the pol_N bit (Bit 2) the input signal is considered active.
- If both pos_edge (Bit 6) and neg_edge (Bit 7) are 0, the whole active signal is considered as an
event, if pos_edge is 1, an event is generated on the inactive->active transition of the signal, if
neg_edge is 1, an event is generated at the active->inactive transition. Two events are generated if
pos_edge and neg_edge are both 1.
- If ignore_AB (Bit 3) is 0, the event is only passed through when the A and B inputs match the pol_A
(Bit 0) and pol_B (Bit 1) bits. If ignore_AB is 1, the event is always passed through.
- Finally, either clr_once (Bit 5) or clr_cont (Bit 4) needs to be set to either pass through only the
next event or all following events.
6.6.4 ENC_STATUS
Only Bit 0 is used in this register, the set status bit indicates that an N event occurred. ENC_STATUS is
not clear-on-read but must be cleared by setting Bit 15 of ENC_MODE.
6.6.5 ENC_X (W)
Writing a value to this register loads the internal position accumulator to this value.
6.6.6 ENC_X (R)
This register contains the encoder position