Datasheet

TMC8460-BI Datasheet (V1.00 / 2016-Sep-01)

6.6 MFCIO Incremental Encoder Unit

The incremental encoder unit allows the decoding of ABN quadrature signals with zero pulse up to a

high speed without CPU load. The parameters for the unit are configurable to fit a wide range of

quadrature encoders. The internal accumulator works as a 48 bit fixed point value with a 32 bit integer

part which is visible through the encoder position register and a 16 bit fractional part which is only

used internally.

Figure 31 - Block structure of the incremental encoder unit

The basic configuration requires the register ENC_CONST to be set to a value matching the encoder.

Advanced configuration options are available in the ENC_MODE register for encoders requiring an

encoder constant with a decimal fraction and to configure the N event detector and the actions taken

at a N event.

6.6.1 Incremental Encoder Unit Signals

Table 137 : MFCIO incremental encoder unit signals

Signal I/O Function

A In Quadrature encoder signal A

B In Quadrature encoder signal B

N In Encoder zero pulse N

6.6.2 Incremental Encoder Unit Register Set

Table 138 : MFCIO incremental encoder unit register set

MFCIO

direct

access

address

Name

R/W

Size

[bit]

Description

0 ENC_MODE W 16

Configuration of incremental encoder unit

Bit 15: clear_status Clears the status flag when written to 1

Bit 10: enc_sel_decimal Fractional part of ENC_CONST is decimal

Bit 8: clr_enc_x ENC_X is set to 0 at N event