Datasheet
TMC8460-BI Datasheet (V1.00 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 119
The configuration for the step/direction registers (12-17) with EtherCAT access is straightforward. All
writable registers except for 16 – SD_DLY – should be updated when the value changes, their
configuration byte is 0x1E. The readable register 13 – SD_SC – can be used with a transparent shadow
register and configuration 0x10. This part of the configuration data is
0x1E101E1E001E
.
In the PWM unit, which is only accessed via SPI, the bit for enabling EtherCAT access stays 0. All
registers are writable and the shadow registers should be updated when the data changes. With the
exception of the registers mentioned above, all configuration bytes are 0x0E, resulting in this
configuration data:
0x0E0E0E0E0E00000E00000000000E0E
.
All other configuration bytes are 0x00 after that and can be omitted from the complete configuration
data:
0x0000000000000000000000001E101E1E001E0E0E0E0E0E00000E00000000000E0E00000000000000000000
Step 2:
The memory areas that are used via EtherCAT and thus need SyncManagers cover only the Step/Direction
unit.
Base Address +0x0 +0x1 +0x2 +0x3 +0x4 +0x5 +0x6 +0x7 +0x8 +0x9 +0xA +0xB +0xC
0x4018 SD_SR SD_ST SD_SL SD_DLY SD_CFG
0x4818 SD_SC
The writable registers, covered by the first SyncManager, are in the memory range 0x4018:0x4024. The
two bytes of the unused SD_DLY register are in this area but the padding byte after the SD_CFG register
(0x4025) can be excluded from the SyncManager.
The only readable register, which is the only one in the second SyncManager, is in the memory range
0x4818:0x481B.
The FMMU, SM and PDO configuration from the ESI file looks like this:
<Fmmu Sm="0">Outputs</Fmmu>
<Fmmu Sm="1">Inputs</Fmmu>
<Sm DefaultSize="13" StartAddress="#x4018" ControlByte="#x04" Enable="1">Outputs</Sm>
<Sm DefaultSize="4" StartAddress="#x4818" ControlByte="#x00" Enable="1">Inputs</Sm>
<RxPdo Mandatory="true" Fixed="true" Sm="0">
<Index>#x1601</Index>
<Name>Writable-Registers</Name>
<Entry>
<Index>#x7008</Index>
<SubIndex>0</SubIndex>
<BitLen>32</BitLen>
<Name>SD_SR</Name>
<DataType>UDINT</DataType>
</Entry>
<Entry>
<Index>#x7009</Index>
<SubIndex>0</SubIndex>
<BitLen>32</BitLen>
<Name>SD_ST</Name>
<DataType>UDINT</DataType>
</Entry>
<Entry>
<Index>#x7010</Index>
<SubIndex>0</SubIndex>
<BitLen>16</BitLen>
<Name>SD_SL</Name>
<DataType>UINT</DataType>
</Entry>
<Entry>
<Index>#x7011</Index>
<SubIndex>0</SubIndex>
<BitLen>16</BitLen>
<Name>SD_DLY</Name>
<DataType>UINT</DataType>
</Entry>
<Entry>
<Index>#x7012</Index>
<SubIndex>0</SubIndex>
<BitLen>8</BitLen>
<Name>SD_CFG</Name>
<DataType>USINT</DataType>
</Entry>
</RxPdo>
<TxPdo Mandatory="true" Fixed="true" Sm="1">
<Index>#x1a00</Index>
<Name>Readable-Registers</Name>
<Entry>