Datasheet

TMC8460-BI Datasheet (V1.00 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 114
When (re)configuring the EEPROM from an EtherCAT master system special care must be taken. Not
every master allows writing a category 1 entry to the EEPROM. There are different ways to write this
into the EEPROM for automatically loading the MFCIO block configuration at power-up:
• Use preprogrammed EEPROMs.
• Use a different category, e.g., 2049, first. Then overwrite the upper byte with 0 with a single
EEPROM byte write.
• Use the local microcontroller (if available) and have it connected to the EEPROM via I2C. Hold the
TMC8460 in reset while programming the EEPROM first. Afterwards tristate the local I2C bus so
that the TMC8460 has control over the IC2 interface and release the TMC8460 from reset.
6.4 MFCIO Register Configuration
Each register of the MFCIO block can be configured using an 8-bit EEPROM entry. Sections 6.2 and 6.3
provide information on the individual EEPROM addresses for configuring each MFCIO block register.
The following parameters and syntax are used for every MFCIO register for configuration.
Table 135 : MFCIO register configuration byte
bit 7 6 5 4 3 2 1 0
function Unused / reserved Enable
ECAT
access
Shadow trigger source
MFCIO block registers have 2 stages – a bank of shadow registers and the main registers.
When writing or reading data to/from the MFCIO block register there is always a shadow register in
between. The shadow registers always hold the latest data written by the MFCIO block or by the ECAT
interface. The content of the shadow registers is copied to the main register depending upon
configurable trigger sources.
Bits 3..0 define the when the transfer between a shadow register and the main register of the MFCIO
unit happens. For write registers the data is copied from the shadow register into the MFC unit register,
for read registers, the data is copied from the MFC unit register into the shadow register. Each MFC unit
register has a corresponding shadow register.
For write registers, Bit 4 determines whether the register will be accessed from the ECAT master (1) or
from the MFC CTRL SPI interface (0). Only one interface can write.
For read registers, Bit 4 determines whether the register is also copied to PDRAM to be read by the
ECAT master.
! Read access (not write) from the MFC CTRL SPI interface is always possible both for read and write
registers.
Table 136 : MFCIO register Shadow trigger source configuration
Bits 3..0 Decimal value Trigger source
0000 0 Always triggered
0001 1 SYNC0 signal
0010 2 SYNC1 signal
0011 3 LATCH0 signal
0100 4 LATCH1 signal
0101 5 Start Of Frame (SOF)
0110 6 End Of Frame (EOF)
0111 7 PDI-SPI Chip Select
1000 8 PDI-SPI Chip Deselect
1001 9 MFC-CTRL-SPI Chip Select
1010 10 MFC-CTRL-SPI Chip Deselect