Datasheet

TMC8460-BI Datasheet (V1.00 / 2016-Sep-01)

6 MFCIO Block Register and Functional Description

6.1 MFCIO Block General Information

The MFCIO block is a separate independent function block next to the main ESC data path. It connects

to the ESC via a configuration interface and a memory bridge. It comes with its own SPI interface (MFC

CTRL SPI) to connect to an application controller. Detailed information on the SPI interface protocol and

characteristics is given in section 2.3.

Besides the configuration interface and the memory bridge the MFCIO block uses various status and

control signals coming from the ESC.

Figure 28 - MFCIO block interfaces to ESC PDRAM

The MFCIO block and its functions are based on the register set summarized in 6.2.

Which functional unit is used and which not depends on the application. All functions have dedicated

IO pins on the TMC8460 and can be used at in parallel.

The MFCIO block can be accessed by the EtherCAT master and by a local MCU at the same time. However,

a single register of the MFCIO block can be accessed either only by the ECAT interface or only by the

MFC CTRL SPI interface.

The access rights as well as the update trigger source for all registers are configurable on a per register

base. The configuration of the MFCIO access rights and update trigger sources is located in the ESC RAM

at addresses 0x0580:0x05FF (ESC Parameter RAM). This configuration data is made available to the MFCIO

block using the configuration interface.

If an MFCIO register is configured to be accessed by the ECAT interface, it is directly mapped to a fixed

position in a memory block in the PDRAM using the memory bridge.

Two memory blocks (MB0 and MB1) are defined in the PDRAM – one for writable registers and one for

read-only registers – to have continuous memory regions for which SyncManagers can be configured

to care for, e.g., data consistency.

The MFCIO register contents of all readable registers that can be accessed from ECAT interface are only

updated if the actual state of the EtherCAT state machine is SAFEOP or OP.

The MFCIO register contents of all writable registers that can be accessed from ECAT interface are only

updated if the actual state of the EtherCAT state machine is OP.