Datasheet

TMC8460-BI Datasheet (V1.00 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 108
5.53 Process Data RAM (0x1000:0xFFFF)
The Process Data RAM starts at address 0x1000. The TMC8460 Process Data RAM has a size of 16kBytes.
Table 128: Process Data RAM (0x1000:0x4FFF)
Bytes
Description
ECAT PDI Reset Value
---- Process Data RAM (r/w) (r/w) Random/undefined
NOTE (r/w): Process Data RAM is only accessible if EEPROM was correctly loaded (register 0x0110.0 = 1).
Two constant memory blocks are used for data to and from the MFCIO block when at least one register
is enabled.
The first block from 0x4000 to 0x405F contains the data to be written into the MFCIO block, the second
block from 0x4800 to 0x4823 contains data read from the MFCIO block.
For compatibility, 2 byte registers are placed at even addresses, 4 and 8 byte registers are placed at
addresses 0x…0, 0x…4, 0x…8 or 0x…C. To match these offsets, padding bytes are added in a few places.
Data written to these padding bytes in the first memory block are ignored, the padding bytes of the
second block read 0x00.
To use this data, SyncManagers (SM) should be set up. For simplicity, one SM can be set up for each
memory area to span the whole area. In case only a few registers are used, the SM can span just the
area that is actually used.
Examples for SM using only smaller memory chunks are shown in the next two segments
5.53.1 MFCIO Block ECAT Write Data Memory Block (0x4000:0x405F)
Data in this memory block is written by the ECAT master to the MFCIO block.
Table 129: MFCIO Block ECAT Write Data Memory Block (0x4000:0x405F)
Start
Address
Size
(bytes)
MFCIO Register Name
0x4000 2
ENC_MODE
0x4004 4
ENC_X
0x4008 4
ENC_CONST
0x400C 8
SPI_TX_DATA
0x4014 2
SPI_CONF
0x4016 1
SPI_LENGTH
0x4017 1
SPI_TIME
0x4018 4
SD_SR
0x401C 4
SD_ST
0x4020 2
SD_SL
0x4022 2
SD_DLY
0x4024 1
SD_CFG
0x4026 2
PWM_MAXCNT
0x4028 2
PWM_CHOPMODE
0x402A 1
PWM_ALIGNMENT
0x402B 1
PWM_POLARITIES
0x402C
2 PWM_VALUE_0
0x402E
2 PWM_VALUE_1
0x4030
2
PWM_VALUE_2