Datasheet
TMC8460-BI Datasheet (V100 / 2016-Sep-01)
Copyright © 2016 TRINAMIC Motion Control GmbH & Co. KG 105
Table 120: Register Latch1 Time Positive Edge (0x09C0:0x09C3 [0x09C0:0x09C7])
Bit
Description
ECAT PDI Reset Value
63:0 Register captures System time at the positive
edge of the Latch1 signal.
r(ack)/- r/
(w ack)*
0
NOTE: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which
guarantees reading a consistent value. Reading this register from ECAT clears Latch0 Status 0x09AF[0] if
0x0980.5=0. Writing to this register from ECAT is not possible.
* PDI register function acknowledge by Write command is disabled: Reading this register from PDI if 0x0980.5=1
clears Latch0 Status 0x09AF[0]. Writing to this register from PDI is not possible.
PDI register function acknowledge by Write command is enabled: Writing this register from PDI if 0x0980.5=1
clears Latch0 Status 0x09AF[0]. Writing to this register from PDI is possible; write value is ignored (write 0).
Table 121: Register Latch1 Time Negative Edge (0x09C8:0x09CB [0x09C8:0x09CF])
Bit
Description
ECAT PDI Reset Value
63:0 Register captures System time at the negative
edge of the Latch1 signal.
r(ack)/- r/
(w ack)*
0
NOTE: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which
guarantees reading a consistent value. Reading this register from ECAT clears Latch0 Status 0x09AF[1] if
0x0980.5=0. Writing to this register from ECAT is not possible.
* PDI register function acknowledge by Write command is disabled: Reading this register from PDI if 0x0980.5=1
clears Latch0 Status 0x09AF[1]. Writing to this register from PDI is not possible.
PDI register function acknowledge by Write command is enabled: Writing this register from PDI if 0x0980.5=1
clears Latch0 Status 0x09AF[1]. Writing to this register from PDI is possible; write value is ignored (write 0).