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TMC8460-BI Datasheet (V100 / 2016-Sep-01)

TRINAMIC

Motion Control GmbH & Co. KG

Hamburg, GERMANY

www.trinamic.com

The TMC8460 is an EtherCAT Slave Controller (ESC) used for EtherCAT communication. It provides the

interface for data exchange between EtherCAT master and the slave’s local application controller.

TMC8460 also provides a large set of complex real-time IO features in hardware with focus on motor

and motion control applications and systems.

Focus

• Easiest to use ESC / Simplicity / Industrial

• License-free / requirements for customer

• Robust / Availability / Flexibility

• Automation / Drives / Robotics / Semiconductor / Multi Axis Systems / Motor & Motion Control

Features

• Standard compliant EtherCAT Slave Controller register set with 2 MII ports, 6 FMMU, 6 Sync

Managers, Distributed clocks (64 bit), 16 Kbyte ESC RAM size

• External I²C EEPROM

• SPI Process Data Interface (PDI) with up to 30Mbit/s

• SPI interface for Trinamic Multi-Function and Control IO Block (MFCIO) with up to 30Mbit/s

• Optional Device Emulation mode

• Trinamic Multi-Function and Control IO Block (MFCIO)

o 8 Digital general purpose IO, individually configurable

o Incremental encoder input (ABN), single ended

o Step & direction output with internal step rate generator

o 3-ch PWM block with configurable frequency, duty cycle, dead times

o Generic SPI master interface with up to 4 slaves, e.g., to connect Trinamic ICs

o Configurable IRQ and event signal

o Configurable watchdog for outputs and inputs

o Simple configuration via EEPROM or from MCU

• 16MHz CLK output, e.g., for MCU or Trinamic ICs or other peripherals

• Operating voltages: 3V3 and 1V2

• Industrial temperature range: -40°C to +100°C

• Package: VFGG400, 17mmx17mm Very Fine Pitch Ball Grid Array, 0.8mm pitch

TMC8460-BI

Integrated EtherCAT Slave Controller with

Enhanced Functionality

Summary of content (151 pages)

PAGE 1
TMC8460-BI Datasheet (V100 / 2016-Sep-01) TMC8460-BI Integrated EtherCAT Slave Controller with Enhanced Functionality TRINAMIC® Motion Control GmbH & Co. KG Hamburg, GERMANY www.trinamic.com The TMC8460 is an EtherCAT Slave Controller (ESC) used for EtherCAT communication. It provides the interface for data exchange between EtherCAT master and the slave’s local application controller.
PAGE 2
TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table of Contents TABLE OF CONTENTS ........................................................................................................................................................... 2 LIST OF FIGURES .................................................................................................................................................................. 5 LIST OF TABLES ...............................................................................
PAGE 3
TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.12.1 3.13 Example layout of the TMC8460-Eval ............................................................................................... 49 SOLDERING PROFILE ............................................................................................................................................... 50 4 ETHERCAT ADDRESS SPACE OVERVIEW.............................................................................................................
PAGE 4
TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.49 5.50 SYNCMANAGER (0X0800:0X087F) ........................................................................................................................ 88 DISTRIBUTED CLOCKS (0X0900:0X09FF).............................................................................................................. 92 5.50.1 Receive Times..........................................................................................................................................
PAGE 5
TMC8460-BI Datasheet (V100 / 2016-Sep-01) 6.9.2 6.9.3 6.9.4 6.9.5 6.9.6 6.9.7 6.9.8 6.9.9 6.9.10 6.9.11 6.9.12 6.9.13 PWM_CHOPMODE Configuration Register .................................................................................... 138 PWM_ALIGNMENT Configuration Register.................................................................................... 139 POLARITIES Configuration Register ...............................................................................................
PAGE 6
TMC8460-BI Datasheet (V100 / 2016-Sep-01) FIGURE 18 - SHARED SPI BUS CONFIGURATION .................................................................................................................... 42 FIGURE 19 - EEPROM INTERFACE SIGNALS ........................................................................................................................... 42 FIGURE 20 - RECOMMENDED LAND PATTERN MEASUREMENTS...............................................................................................
PAGE 7
TMC8460-BI Datasheet (V100 / 2016-Sep-01) TABLE 27: REGISTER ESC RESET PDI (0X0041) ................................................................................................................... 60 TABLE 28: REGISTER ESC DL CONTROL (0X0100:0X0103) .................................................................................................. 61 TABLE 29: REGISTER PHYSICAL READ/WRITE OFFSET (0X0108:0X0109) ............................................................................
PAGE 8
TMC8460-BI Datasheet (V100 / 2016-Sep-01) TABLE 83: REGISTER ACTIVATE FMMU Y (0X06YC).............................................................................................................. 87 TABLE 84: REGISTER RESERVED FMMU Y (0X06YD:0X06YF) ............................................................................................... 87 TABLE 85: SYNCMANAGER REGISTER OVERVIEW....................................................................................................................
PAGE 9
TMC8460-BI Datasheet (V100 / 2016-Sep-01) TABLE 139 : LIST OF TYPICAL ENCODER CONSTANTS ............................................................................................................ 123 TABLE 140 : MFCIO MASTER UNIT SIGNALS ........................................................................................................................ 125 TABLE 141 : MFCIO SPI MASTER UNIT REGISTER SET ....................................................................................................
PAGE 10
TMC8460-BI Datasheet (V100 / 2016-Sep-01) 1 Abbreviations AL BOOT CS ECAT EEPROM ENI EoF ESC ESI ETG EtherCAT FCS FMMU GPI GPO I2C INIT IRQ MAC MCU MFCIO MI MII OP PDI PDO PHY PREOP PWM RAM RX SAFEOP SII SM SoF SPI TX µC XML S/D PDRAM MBx IEC ESM Special boot state of the EtherCAT state machine Chip Select (SPI bus signal) EtherCAT (or sometimes used for EtherCAT Master Interface) Electrically Erasable Programmable Read Only Memory. Non-volatile memory used to store EtherCAT Slave Information (ESI).
PAGE 11
TMC8460-BI Datasheet (V100 / 2016-Sep-01) 2 Principles of Operation 2.1 Key Concepts 2.1.1 General Information on EtherCAT EtherCAT (Ethernet in Control and Automation Technology) has been developed and patented by Beckhoff. It is an Ethernet-based technology for data transmission and application control in real time. All process data for all connected nodes are transmitted in a single frame. All nodes connected to the bus interpret, process, and modify their data „on the fly“.
PAGE 12
TMC8460-BI Datasheet (V100 / 2016-Sep-01) 2.1.3 Trinamic Multi-Function and Control IO Block Besides the proven EtherCAT functionality and the main EtherCAT data path, TMC8460 comes with a dedicated hardware block providing a configurable set of complex real-time IO functions to smart embedded systems. This IO functionality is called Multi-Function Control and IO block – MFCIO. Its special focus is on motor and motion control applications and systems while it is not limited to this application area.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) WATCHDOG • • • • Configurable for all inputs and outputs Outputs will be assigned with configurable level @ watchdog event Inputs will trigger a watchdog event only ECAT SoF and PDI SPI Chip Select can be monitored with watchdog as well EMERGENCY SWITCH INPUT • • 2.2 If used all functional outputs are set to a configurable safe state when the switch is not actively driven high Low active: must be pulled high for normal operation if used.
PAGE 14
TMC8460-BI Datasheet (V100 / 2016-Sep-01) 2.3.5 Configuration Inputs External package pins allow for selection of configuration options that typically do not change during operation by directly connecting them to 3V3 or ground. These package pins can also be controlled by GPIOs of the local application controller.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Figure 1 - TMCL-IDE with direct register access to the TMC8460-BI on its evaluation board A wizard helps and simplifies the configuration and setup of the TMC8460-BI to your specific needs and provides code examples for your configuration to be used inside you microcontroller firmware and the EEPROM for startup configuration. Copyright © 2016 TRINAMIC Motion Control GmbH & Co.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3 Device Usage and Handling 3.1 Sample Block Diagrams The TMC8460 allows for flexible system architectures using a microcontroller running the Slave Stack Code (SSC) or using Device Emulation mode without a microcontroller. The following examples show typical system architectures using the TMC8460. 3.1.1 Typical EtherCAT Slave architecture The first application diagram shows the TMC8460 in a typical straightforward architecture.
PAGE 21
TMC8460-BI Datasheet (V100 / 2016-Sep-01) 25MHz source RXTX RJ45 + Transformer RXTX 100 Mbit ETH PHY 100 Mbit ETH PHY EEPROM I2C I2C MII TMC8460-BI PDI SPI MFCIO Block SPI MII DIGI IO nES ABN SPI 16MHz CLK Incr. Encoder Input µC / Application Controller with Slave Stack Code TMC Motion Contr. Other application parts TMC Driver TMC Driver 16MHz CLK Figure 7 - Application diagram using the MFCIO block features to reduce software overhead and provide real-time hardware support to the MCU.
PAGE 22
TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.2 3.2.1 Samples Circuits IC supply Only a minimal amount of decoupling capacitors is shown here. If possible every supply pin (1.2V and 3.3V) should have a separate 100nF capacitor connected between it and GND as close to the pin as possible. Larger capacitor values can be used on the 3.3V and 1.2V supply rails for increased stability. 3.2.
PAGE 23
TMC8460-BI Datasheet (V100 / 2016-Sep-01) LATCH_IN0, LATCH_IN1, SYNC_OUT0, SYNC_OUT1, NRST_OUT, EN_16MHZ_OUT and CLK_16MHZ_OUT are optional signals that can be used depending on the specific use case. Configuration Pins with their setting in this example: LINK_POLARITY 1 (+3.3V) MII_LINK signal from PHYs is high active PHY_OFFSET 0 (GND) PHY address offset is 0 PROM_SIZE 1 (+3.3V) EEPROM is 32kbit or larger (4Mbit max.
PAGE 24
TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.2.6 MFC I/Os The I/Os of the MFC block are shown unconnected here as the actual connections depend on the intended use. Copyright © 2016 TRINAMIC Motion Control GmbH & Co.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.3 Pinout and Pin Description The following table contains the pin description and required pin connections of the TMC8460-BI for the Very Fine Ball Pitch Grid Array package VF400. Pins not listed in this table are not connected (n.c.) / leave open. PKG.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) F15 LED_RUN E3 PDI_EMULATION F3 PDI_EOF G3 PDI_SHARED_SPI_BU S F4 PDI_SOF C1 PDI_SPI_CSN C2 PDI_SPI_IRQ E2 PDI_SPI_MISO E1 PDI_SPI_MOSI D2 PDI_SPI_SCK E5 H5 PDI_WD_STATE PDI_WD_TRIGGER H6 MFC_CTRL_SPI_CSN F7 MFC_CTRL_SPI_MISO F6 MFC_CTRL_SPI_MOSI G6 MFC_CTRL_SPI_SCK F5 MFCIO_IRQ T15 MFC_ABN_A MFC_ABN_B MFC_ABN_N MFC_GPIO[0] MFC_GPIO[1] T14 U14 J15 K15 Run Status LED, connect to green LED (Cathode) 0 = LED on, 1 = LED off Selects b
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) N15 MFC_GPIO[2] MFC_GPIO[3] MFC_GPIO[4] I/O MFCIO block GPIO port, configurable I/O MFCIO block GPIO port, configurable I/O MFCIO block GPIO port, configurable K16 MFC_GPIO[5] I/O MFCIO block GPIO port, configurable L16 Y13 MFC_GPIO[6] MFC_GPIO[7] MFC_PWM_HS_0 MFC_PWM_HS_1 MFC_PWM_HS_2 MFC_PWM_LS_0 MFC_PWM_LS_1 MFC_PWM_LS_2 I/O I/O O O O O O O V14 MFC_nES I U13 MFC_PWM_PULSE_A O U18 MFC_PWM_PULSE_AB O U11 MFC_PWM_PULSE_B O W10 MFC_PWM_PULSE_C
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) G19 MII1_RXD[1] I MII interface to PHY of link in port F20 MII1_RXD[2] I MII interface to PHY of link in port F19 J19 MII1_RXD[3] MII1_RXDV MII1_RXER I I I J18 MII1_TX_SHIFT[0] I G18 MII1_TX_SHIFT[1] I D20 T19 MII1_TXCLK MII1_TXD[0] MII1_TXD[1] MII1_TXD[2] MII1_TXD[3] MII1_TXEN MII2_LINK MII2_RXCLK MII2_RXD[0] MII2_RXD[1] MII2_RXD[2] I O O O O O I I I I I MII interface to PHY of link in port MII interface to PHY of link in port MII interface to
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Use 4K7 pull up resistor to 3.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) M20 N14 P14 P16 P5 P6 R14 R19 T11 T12 U15 V18 W11 W17 Y14 Y17 A12 A2 B15 B5 C18 C8 D1 D11 E14 E4 F17 G11 G13 G20 G9 H10 H12 H13 H3 H7 H8 J11 J13 J16 J9 K10 +3V3 (VCCIO) +3V3 (VCCIO) +3V3 (VPP) +3V3 (VCCIO) +3V3 (VPP) +3V3 (PLL) +3V3 (VCCIO) +3V3 (VCCIO) +3V3 (VPP) +3V3 (VCCIO) +3V3 (VCCIO) +3V3 (VCCIO) +3V3 (VCCIO) +3V3 (VPP) +3V3 (VCCIO) +3V3 (VPP) GND GND GND GND GND GND GND GND GND GND GND GND GND (PLL) GND GND GND GND GND GND GND (PLL) GND GND GND GND GND GND
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) K12 K14 K19 K8 L11 L13 L2 L9 M10 M12 M14 M5 M8 N11 N13 N18 N5 N7 N9 P1 P10 P12 P4 P8 R6 R9 T1 T10 T16 T17 T2 T3 T4 T5 T6 T7 T9 U1 U10 U2 U20 U3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND (PLL) GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Copyright © 2016 TRINAMIC Motion Control GmbH & Co.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) U4 U6 U7 U8 U9 V1 V10 V13 V2 V3 V4 V5 V6 V7 V8 V9 W1 W16 W3 W5 W7 W9 Y1 Y19 Y3 Y5 Y7 Y9 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Copyright © 2016 TRINAMIC Motion Control GmbH & Co.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.4 Ethernet PHYs The TMC8460-BI requires Ethernet PHYs with MII interface. The MII interface of the TMC8460 is optimized for low additional delays by omitting a transmit FIFO. Therefore, additional requirements to Ethernet PHYs exist and not every Ethernet PHY is suited. Therefore, please see the Ethernet PHY Selection Guide provided by the ETG: http://download.beckhoff.com/download/Document/EtherCAT/Development_products/AN_PHY_Selection_ GuideV2.3.pdf.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) MIIx_RXDV MIIx_RXER MIIx_TXEN MIIx_TXCLK MIIx_TXD[3:0] MCLK MDIO 3.4.2 Receive data valid Receive error Transmit enable Transmit clock (optional for automatic TX shift) Transmit data Management Interface clock, MCLK is driven rail-to-rail, idle value is High. Management Interface data, MDIO must have a pull-up resistor (4.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) TMC8460 PDI_SPI_SCK PDI_SPI_CSN PDI_SPI_MOSI PDI_SPI_MISO PDI_IRQ PDI_SOF PDI_EOF PDI_EMULATION PDI_WD_STATE PDI_WD_TRIGGER Figure 10 - PDI SPI Interface Signals Table 2 : PDI SPI interface signal description and connection TMC8460 pin PDI_SPI_SCK PDI_SPI_CSN PDI_SPI_MOSI PDI_SPI_MISO PDI_IRQ PDI_EMULATION PDI_SOF PDI_EOF PDI_WD_STATE PDI_WD_TRIGGER Usage/description SPI master clock SPI chip select for the TMC8460 PDI Master out slave in data Master in slave
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 1 1 1 1 0 0 1 1 0 1 0 1 Write Reserved Address extension, signaling 3 byte mode Reserved Figure 11 - 2 byte addressing mode Figure 12 - 3 byte addressing mode Unless highest performance is required, using only the 3-byte addressing mode and the read with wait state command is recommended since it reduces the need for special cases in the software.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) COMMAND 3 – READ WITH WAIT STATE BYTE This command is similar to the Read command with an added dummy byte between the address/command part and the data part of the datagram. This allows enough time to fetch the data in any case.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.5.2 Timing example This example shows a generic read access with wait state and 2 byte addressing. All configurable options are shown. The delays between the transferred bytes are just to show the byte boundaries and are not required. Figure 13 - PDI SPI timing example Copyright © 2016 TRINAMIC Motion Control GmbH & Co.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.6 MFC CTRL SPI The MFC Control SPI is a SPI mode 3 slave with low active chip select. It allows an external microcontroller to access the MFC registers. The SPI clock frequency can be up to 30MHz. The following diagram shows all signals related to the MFC CTRL SPI interface.
PAGE 41
TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.6.1 Timing example This example shows a generic MFC register read access with wait state. The delays between the transferred bytes are just to show the byte boundaries and are not required. Figure 17 - MFC Control SPI timing example 3.6.2 Sharing Bus Lines with PDI SPI Copyright © 2016 TRINAMIC Motion Control GmbH & Co.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) To reduce overall number of signals on the PCB or if the local application controller has only one SPI interface, the MFC CTRL SPI bus can use the SPI bus signals of the PDI SPI. Therefore, both interfaces are internally switched on the PDI SPI interface. The original MFC CTRL SPI signals (MOSI, MISO, and SCK) remain unconnected in this case. Only the MFC_CTRL_SPI_CSN pin/signal must be used if the MFCIO block should be accessed.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) TMC8460 pin PROM_DATA PROM_CLK PROM_SIZE EEPROM_OK 3.8 Usage/description I2C data, requires pull-up I2C clock, requires pull-up Configures EEPROM size Indicates that EEPROM has be successfully loaded, this may be useful for the local application controller Vendor ID, ESC Type, ESC Revision and Build History Trinamic owns a dedicated EtherCAT vendor ID and holds a specific ID for Trinamic EtherCAT slave controllers to distinguish from other ESC manufacturers.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.9 Electrical Characteristics 3.9.1 Operating Conditions Stresses beyond those listed in the following table may cause damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings are stress ratings only.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.9.4 Power Consumption The values given here are typical values only. The real values depend on configuration, activity, and temperature.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.10 Marking and Order Codes Type TMC8460-BI Code & Marking Package TMC8460-BI VFG400 TMC8460-EVAL TMC8460-EVAL PCB Landungsbruecke Landungsbruecke PCB Eselsbruecke Eselsbruecke PCB Temperature Range -40°C ... +100°C Description Size [mm2] 17 x 17 EtherCAT slave controller with enhanced features Evaluation board for 85 x 79 TMC8560-BI EtherCAT slave controller Baseboard for TMC8460-EVAL 85 x 55 and further evaluation boards.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.12 Layout Considerations Mask hole dia. 0.45mm Pa di d t 0 . s ta o v 56 nc i a m e m Via hole dia. 0.25mm Pad dia. 0.3mm th id w e ac m m Tr .15 0 Pad distance 0.8mm The required board area for the TMC8460, EEPROM, PHYs, capacitors and LEDs is below 12.5cm2 on a sixlayer board. For best soldering results, only the BGA pads should be exposed under the TMC8460, while vias, traces and ground/power planes should be covered by the soldermask.
PAGE 49
TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.12.1 Example layout of the TMC8460-Eval Figure 21 - Top layer (1) Figure 22 - Inner layer (2) Figure 23 - Inner layer (3) Figure 24 - Inner layer (4) Figure 25 - Inner layer (5) Figure 26 - Bottom layer (6) Copyright © 2016 TRINAMIC Motion Control GmbH & Co.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 3.13 Soldering Profile The provided reflow soldering profile in accordance to IPC/JEDEC standard J-STD-020 is for reference only. Trinamic advises to optimize to the respective board level parameters to get proper reflow outcome.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 4 EtherCAT Address Space Overview An EtherCAT Slave Controller (ESC) has an address space of 64Kbyte. The first block of 4Kbyte (0x0000:0x0FFF) is dedicated for ESC- and EtherCAT-relevant configuration and status registers. The PDRAM starts at address 0x1000. The TMC8460-BI has a PD-RAM size of 16 Kbyte. The following table lists the standard ESC register set which is also available in the TMC8460-BI. Section 5 contains a detailed register description.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Address1 0x0140 0x0141 0x014E:0x014F 0x0150 0x0151 0x0152:0x0153 0x0200:0x0201 0x0204:0x0207 0x0210:0x0211 0x0220:0x0223 Length (Byte) Description 1 1 2 1 1 2 PDI / ESC Configuration PDI Control ESC Configuration PDI Information PDI Configuration SYNC/LATCH[1:0] PDI Configuration Extended PDI Configuration 2 4 2 4 Interrupts ECAT Event Mask PDI AL Event Mask ECAT Event Request AL Event Request 0x0300:0x0307 0x0308:0x030B 0x030C 0x030D 0x030E 0x0310:0x0313
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 0x0518:0x051B Length (Byte) 4 0x0580:0x05FF 0x0580:0x05AB 128 43 0x0600:0x06FF +0x0:0x3 +0x4:0x5 +0x6 +0x7 +0x8:0x9 +0xA +0xB +0xC +0xD:0xF 16x16 4 2 1 1 2 1 1 1 3 Address1 Description PHY Port Status ESC Parameter Ram TMC8460 MFCIO block configuration Can be written at start-up from EEPROM configuration (with category 1) or by ECAT or PDI at runtime.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Address1 0x0800:0x087F +0x0:0x1 +0x2:0x3 +0x4 +0x5 +0x6 +0x7 Length (Byte) 16x2 2 2 1 1 1 1 0x0900:0x09FF 0x0900:0x0903 0x0904:0x0907 0x0908:0x090B 0x090C:0x090F 4 4 4 4 0x0910:0x0917 0x0918:0x091F 0x0920:0x0927 0x0928:0x092B 0x092C:0x092F 0x0930:0x0931 0x0932:0x0933 0x0934 0x0935 0x0936 4/8 4/8 4/8 4 4 2 2 1 1 1 0x0980 1 0x0981 0x0982:0x0983 0x0984 0x098E 0x098F 0x0990:0x0997 0x0998:0x099F 0x09A0:0x09A3 0x09A4:0x09A7 1 2 1 1 1 4/8 4/8 4 4 0x09A8 0x09A9 0
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Address1 0x09AF 0x09B0:0x09B7 0x09B8:0x09BF 0x09C0:0x09C7 0x09C8:0x09CF Length (Byte) 1 4/8 4/8 4/8 4/8 Description Latch1 Latch0 Latch0 Latch1 Latch1 Status Time Positive Edge Time Negative Edge Time Positive Edge Time Negative Edge DC – SyncManager Event Times EtherCAT Buffer Change Event Time PDI Buffer Start Event Time PDI Buffer Change Event Time 0x09F0:0x09F3 0x09F8:0x09FB 0x09FC:0x09FF 4 4 4 0x0E00:0x0EFF 256 ESC specific TMC8460 Product and Vendor
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5 EtherCAT Register Description 5.1 Type (0x0000) Table 12: Register Type (0x0000) Description Type of EtherCAT controller Bit 7:0 5.2 ECAT PDI Reset Value r/- r/- Trinamic ESC Type: 0xD0 ECAT PDI Reset Value r/- r/- TMC8460: 0x60 TMC8461: 0x61 ECAT PDI Reset Value r/- r/- TMC8460: 0x02 = Version 1.0 Revision (0x0001) Table 13: Register Revision (0x0001) Description Revision of EtherCAT controller. Bit 7:0 5.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 7:0 5.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 7 8 Description ECAT PDI Reset Value Separate Handling of FCS Errors: 0: Not supported 1: Supported, frames with wrong FCS and additional nibble will be counted separately in Forwarded RX Error Counter r/- r/- TMC8460: 1 Enhanced DC SYNC Activation 0: Not available 1: Available r/- r/- TMC8460: 1 NOTE: This feature refers to registers 0x981[7:3], 0x0984 9 EtherCAT LRW command support: 0: Supported 1: Not supported r/- r/- TMC8460: 0 10 Ethe
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.11 Write Register Enable (0x0020) This register/function is not available with TMC8460-BI. Table 22: Register Write Register Enable (0x0020) Bit 0 7:1 Description If write register protection is enabled, this register has to be written in the same Ethernet frame (value does not care) before other writes to this station are allowed. Write protection is still active after this frame (if Write Register Protection register is not changed).
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 0 7:1 Description If ESC write protection is enabled, this register has to be written in the same Ethernet frame (value does not care) before other writes to this station are allowed. ESC write protection is still active after this frame (if ESC Write Protection register is not changed). Reserved, write 0 ECAT PDI Reset Value r/w r/- 0 r/- r/- 0 5.14 ESC Write Protection (0x0031) This register/function is not available with TMC8460-BI.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit Write 7:0 Read 1:0 7:2 Description ECAT PDI Reset Value A reset is asserted after writing 0x52 (‘R’), 0x45 (‘E’) and 0x53 (‘S’) in this register with 3 consecutive commands. r/- r/w 0 Progress of the reset procedure: 01: after writing 0x52 10: after writing 0x45 (if 0x52 was written before) 00: else Reserved, write 0 r/- r/w 00 r/- r/- 0 5.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 13:12 Description ECAT PDI Reset Value Loop Port 2: 00: Auto 01: Auto Close 10: Open 11: Closed r/w* r/- 00 15:14 Loop Port 3: 00: Auto 01: Auto Close 10: Open 11: Closed r/w* r/- 00 18:16 RX FIFO Size (ESC delays start of forwarding until FIFO is at least half full).
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 15:0 Description Offset of R/W Commands (FPRW, APRW) between Read address and Write address. RD_ADR = ADR and WR_ADR = ADR + R/W-Offset ECAT PDI Reset Value r/w r/- 0 5.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 12 Description ECAT PDI Reset Value Loop Port 2: 0: Open 1: Closed r*/- r/- 0 13 Communication on Port 2: 0: No stable communication 1: Communication established r*/- r/- 0 14 Loop Port 3: 0: Open 1: Closed r*/- r/- 0 15 Communication on Port 3: 0: No stable communication 1: Communication established r*/- r/- 0 * Reading DL Status register from ECAT clears ECAT Event Request 0x0210[2].
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Description ECAT PDI Reset Value Actual State of the Device State Machine: 1: Init State 3: Request Bootstrap State 2: Pre-Operational State 4: Safe-Operational State 8: Operational State r*/- r/(w) 1 4 Error Ind: 0: Device is in State as requested or Flag cleared by command 1: Device has not entered requested State or changed State as result of a local action r*/- r/(w) 0 5 Device Identification: 0: Device Identification not valid 1: Device Identific
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) This register/function is not available with TMC8460-BI. Table 36: Register ERR LED Override (0x0139) Bit 3:0 4 7:5 Description LED code: 0x0: Off 0x1-0xC: Flash 1x – 12x 0xD: Blinking 0xE: Flickering 0xF: On Enable Override: 0: Override disabled 1: Override enabled Reserved, write 0 ECAT PDI Reset Value r/w r/w 0 r/w r/w 0 r/w r/w 0 NOTE: New error conditions will disable ERR LED Override (0x0139[4]=0).
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 7:0 Description ECAT PDI Reset Value Process data interface: 0x00: Interface deactivated (no PDI) 0x01: 4 Digital Input 0x02: 4 Digital Output 0x03: 2 Digital Input and 2 Digital Output 0x04: Digital I/O 0x05: SPI Slave 0x06: Oversampling I/O 0x07: EtherCAT Bridge (port 3) 0x08: 16 Bit asynchronous Microcontroller interface 0x09: 8 Bit asynchronous Microcontroller interface 0x0A: 16 Bit synchronous Microcontroller interface 0x0B: 8 Bit synchronous Microcon
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 7 Description ECAT PDI Enhanced Link port 3: 0: disabled (if bit 1=0) 1: enabled r/- r/- Reset Value 5.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) ECAT PDI Reset Value r/- r/- TMC8460: 3 SPI_IRQ output driver/polarity: 00: Push-Pull active low 01: Open Drain (active low) 10: Push-Pull active high 11: Open Source (active high) r/- r/- 4 SPI_SEL polarity: 0: Active low 1: Active high r/- r/- 5 Data Out sample mode: 0: Normal sample (SPI_DO and SPI_DI are sampled at the same SPI_CLK edge) 1: Late sample (SPI_DO and SPI_DI are sampled at different SPI_CLK edges) r/- r/- Reserved, set EEPROM value
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Description ECAT PDI Reset Value SYNC0 output driver/polarity: 00: Push-Pull active low 01: Open Drain (active low) 10: Push-Pull active high 11: Open Source (active high) r/- r/- TMC8460: 10 2 SYNC0/LATCH0 configuration*: 0: LATCH0 Input 1: SYNC0 Output r/- r/- TMC8460: 1 3 SYNC0 mapped to AL Event Request register 0x0220.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 31:0 Description AL Event masking of the AL Event Request register Events for mapping to PDI IRQ signal: 0: Corresponding AL Event Request register bit is not mapped 1: Corresponding AL Event Request register bit is mapped ECAT PDI Reset Value r/- r/w 0x00FF:0xFF0F 5.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Description ECAT PDI Reset Value AL Control event: 0: No AL Control Register change 1: AL Control Register has been written2 (Bit is cleared by reading AL Control register 0x0120:0x0121 from PDI) r/- r/- 0 1 DC Latch event: 0: No change on DC Latch Inputs 1: At least one change on DC Latch Inputs (Bit is cleared by reading DC Latch event times from PDI, so that Latch 0/1 Status 0x09AE:0x09AF indicates no event.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.33 RX Error Counter (0x0300:0x0307) Errors are only counted if the corresponding port is enabled. Table 47: Register RX Error Counter Port y (0x0300+y*2:0x0301+y*2) Bit 7:0 15:8 Description Invalid frame counter of Port y (counting is stopped when 0xFF is reached). RX Error counter of Port y (counting is stopped when 0xFF is reached). This is coupled directly to RX ERR of MII interface/EBUS interface.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 2:0 3 4 5 7:6 Description SPI access which caused last PDI Error. Number of SPI clock cycles of whole access (modulo 8) Busy violation during read access Read termination missing Access continued after read termination byte SPI command CMD[2:1] ECAT PDI Reset Value r/- r/- 0 NOTE: Error Counter 0x030D and Error Code 0x030E are cleared if error counter 0x030D is written. Write value is ignored (write 0). 5.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 15:0 Description Watchdog Time Process Data: number of basic watchdog increments (Default value with Watchdog divider 100µs means 100ms Watchdog) ECAT PDI Reset Value r/w r/- 0x03E8 There is one Watchdog for all SyncManagers. Watchdog is disabled if Watchdog time is set to 0x0000. Watchdog is restarted with every write access to SyncManagers with Watchdog Trigger Enable Bit set. 5.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Register Address Length (Byte) 0x0501 1 EEPROM PDI Access State 0x0502:0x0503 2 EEPROM Control/Status 0x0504:0x0507 4 EEPROM Address 0x0508:0x050F 4/8 Description EEPROM Data EtherCAT controls the SSI EEPROM interface if EEPROM configuration register 0x0500.0=0 and EEPROM PDI Access register 0x0501.0=0, otherwise PDI controls the EEPROM interface. In EEPROM emulation mode, the PDI executes outstanding EEPROM commands.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 62: Register EEPROM Control/Status (0x0502:0x0503) Bit 0 Description ECAT PDI Reset Value ECAT write enable*2: 0: Write requests are disabled 1: Write requests are enabled This bit is always 1 if PDI has EEPROM control.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Errors can be indicated by writing a 1 into the error bit 0x0502.13. Acknowledging clears AL Event Request 0x0220[5]. * Write Enable bit 0 is self-clearing at the SOF of the next frame, Command bits [10:8] are self-clearing after the command is executed (EEPROM Busy ends). Writing “000” to the command register will also clear the error bits [14:13]. Command bits [10:8] are ignored if Error Acknowledge/Command is pending (bit 13).
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.45.1 EEPROM emulation with TMC8460 Write access to EEPROM Data register 0x0508:0x050F is possible if EEPROM interface is busy (0x0502.15=1). PDI places EEPROM read data in this register before the pending EEPROM Read command is acknowledged (writing to 0x0502[10:8]). For Reload command: place the following information in the EEPROM Data register before acknowledging the command.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) PDI controls the MII management interface if MII Management PDI Access register 0x0517.0=1, otherwise EtherCAT controls the MII management interface. Copyright © 2016 TRINAMIC Motion Control GmbH & Co.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 67: Register MII Management Control/Status (0x0510:0x0511) Bit 0 1 2 7:3 9:8 12:10 13 14 15 Description ECAT PDI Reset Value Write enable*: 0: Write disabled 1: Write enabled This bit is always 1 if PDI has MI control.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 68: Register PHY Address (0x0512) Bit 4:0 6:5 7 Description PHY Address Reserved, write 0 Show configured PHY address of port 0-3 in register 0x0510[7:3]. Select port x with bits [4:0] of this register (valid values are 0-3): 0: Show address of port 0 (offset) 1: Show individual address of port x ECAT PDI Reset Value r/(w) r/r/(w) r/(w) r/r/(w) 0 0 NOTE: r/ (w): write access depends on assignment of MI (ECAT/PDI).
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 72: Register MII Management PDI Access State (0x0517) Bit 0 1 7:2 Description ECAT PDI Reset Value Access to MII management: 0: ECAT has access to MII management 1: PDI has access to MII management r/- r/(w) 0 Force PDI Access State: 0: Do not change Bit 517.0 1: Reset Bit 517.0 to 0 r/w r/- 0 Reserved, write 0 r/- r/- 0 NOTE: r/ (w): assigning access to PDI (bit 0 = 1) is only possible if 0x0516.0=0 and 0x0517.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.47 Parameter RAM (0x0580:0x05AB) for TMC8460 MFCIO Block Configuration The content of these registers can be automatically loaded from EEPROM after reset/power-up. Therefore, the configuration date in the EEPROM must contain a section with category 1 and the appropriate configuration vector. There are 44 MFCIO registers. Each byte configures one of the MFCIO registers. y is in the range of 0 to 43 and is used as offset with respect to address 0x0580.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.48 FMMU (0x0600:0x06FF) Each FMMU entry is described in 16 Bytes from 0x0600:0x060F to 0x06F0:0x06FF. y is the FMMU index. The TMC8460-BI supports up to 6 FMMUs. Thus TMC8460-BI supports y=0…5.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 2:0 7:3 Description Last logical bit that shall be mapped (bits are counted from least significant bit (=0) to most significant bit(=7) Reserved, write 0 ECAT PDI Reset Value r/w r/- 0 r/- r/- 0 Table 80: Register Physical Start address FMMU y (0x06y8-0x06y9) Bit 15:0 Description Physical Start Address (mapped to logical Start address) ECAT PDI Reset Value r/w r/- 0 Table 81: Register Physical Start bit FMMU y (0x06yA) Bit 2:0 7:3 Descri
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.49 SyncManager (0x0800:0x087F) SyncManager registers are mapped from 0x0800:0x0807 to 0x0818:0x087F. y specifies the SyncManager number. The TMC8460-BI supports up to 6 SyncManagers. Thus TMC8460-BI supports y=0…5.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 88: Register Control Register SyncManager y (0x0804+y*8) Bit 1:0 Description ECAT PDI Reset Value Operation Mode: 00: Buffered (3 buffer mode) 01: Reserved 10: Mailbox (Single buffer mode) 11: Reserved r/(w) r/- 00 3:2 Direction: 00: Read: ECAT read access, PDI write access. 01: Write: ECAT write access, PDI read access.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 89: Register Status Register SyncManager y (0x0805+y*8) Bit 0 Description ECAT PDI Reset Value Interrupt Write: 1: Interrupt after buffer was completely and successfully written 0: Interrupt cleared after first byte of buffer was read r/- r/- 0 r/- r/- 0 NOTE: This interrupt is signaled to the reading side if enabled in the SM Control register.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 90: Register Activate SyncManager y (0x0806+y*8) Description ECAT PDI Reset Value SyncManager Enable/Disable: 0: Disable: Access to Memory without SyncManager control 1: Enable: SyncManager is active and controls Memory area set in configuration r/w r/ (w ack)* 0 Repeat Request: A toggle of Repeat Request means that a mailbox retry is needed (primarily used in conjunction with ECAT Read Mailbox) r/w r/ (w ack)* 0 Reserved, write 0 r/- 0 6 Lat
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 91: Register PDI Control SyncManager y (0x0807+y*8) Bit 0 Description ECAT PDI Reset Value Deactivate SyncManager: Read: 0: Normal operation, SyncManager activated. 1: SyncManager deactivated and reset SyncManager locks access to Memory area.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 63:0 Description ECAT PDI Reset Value Local time of the beginning of a frame (start first bit of preamble) received at the ECAT Processing Unit containing a write access to Register 0x0900 r/- r/- Undefined NOTE: E.g., if port 0 is open, this register reflects the Receive Time Port 0 as a 64 Bit value. Copyright © 2016 TRINAMIC Motion Control GmbH & Co.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.50.2 Time Loop Control Unit Time Loop Control unit is usually assigned to ECAT. Write access to Time Loop Control registers by PDI (and not ECAT) is only possible with explicit configuration. Table 95: Register System Time (0x0910:0x0913 [0x0910:0x0917]) Bit 63:0 63:0 31:0 Description ECAT read access: Local copy of the System Time when the frame passed the reference clock (i.e., including System Time Delay).
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 97: Register System Time Delay (0x0928:0x092B) Bit 31:0 Description Delay between Reference Clock and the ESC ECAT PDI Reset Value r/(w) r/(w) 0 NOTE: Write access to this register depends upon ESC configuration (typically ECAT, PDI only with explicit ESC configuration: System Time PDI controlled). Reset internal system time difference filter and speed counter filter by writing Speed Counter Start (0x0930:0x0931) after changing this value.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 101: Register System Time Difference Filter Depth (0x0934) Bit 3:0 7:4 Description Filter depth for averaging the received System Time deviation TMC8460: A write access resets System Time Difference (0x092C:0x092F) Reserved, write 0 ECAT PDI Reset Value r/(w) r/(w) 4 r/- r/- 0 NOTE: Write access to this register depends upon ESC configuration (typically ECAT, PDI only with explicit ESC configuration: System Time PDI controlled).
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 103: Register Receive Time Latch Mode (0x0936) Bit 0 7:1 Description Receive Time Latch Mode: 0: Forwarding mode (used if frames are entering the ESC at port 0 first): Receive time stamps of ports 1-3 are enabled after the write access to 0x0900, so the following frame at ports 1-3 will be time stamped (this is typically the write frame to 0x0900 coming back from the network behind the ESC).
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.50.3 Cyclic Unit Control Table 104: Register Cyclic Unit Control (0x0980) Bit 0 Description ECAT PDI Reset Value SYNC out unit control: 0: ECAT controlled 1: PDI controlled r/w r/- 0 3:1 Reserved, write 0 r/- r/- 0 Latch In unit 0: 0: ECAT controlled 1: PDI controlled r/w r/- 0 r/w r/- 0 r/- r/- 0 4 NOTE: Always 1 (PDI controlled) if System Time is PDI controlled.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.50.4 SYNC Out Unit Table 105: Register Activation register (0x0981) Description ECAT PDI Reset Value Sync Out Unit activation: 0: Deactivated 1: Activated r/(w) r/(w) 0 1 SYNC0 generation: 0: Deactivated 1: SYNC0 pulse is generated r/(w) r/(w) 0 2 SYNC1 generation: 0: Deactivated 1: SYNC1 pulse is generated r/(w) r/(w) 0 3 Auto-activation by writing Start Time Cyclic Operation (0x0990:0x0997): 0: Disabled 1: Auto-activation enabled. 0x0981.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 0 1 2 7:3 Description ECAT PDI Reset Value SYNC0 activation state: 0: First SYNC0 pulse is not pending 1: First SYNC0 pulse is pending r/- r/- 0 SYNC1 activation state: 0: First SYNC1 pulse is not pending 1: First SYNC1 pulse is pending Start Time Cyclic Operation (0x0990:0x0997) plausibility check result when Sync Out Unit was activated: 0: Start Time was within near future 1: Start Time was out of near future (0x0981.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Bit 63:0 Description Write: Start time (System time) of cyclic operation in ns Read: System time of next SYNC0 pulse in ns ECAT PDI Reset Value r/(w) r/(w) 0 NOTE: Write to this register depends upon setting of 0x0980.0. Only writable if 0x0981.0=0. Auto-activation (0x0981.3=1): upper 32 bits are automatically extended if only lower 32 bits are written within one frame.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.50.5 Latch In unit Table 114: Register Latch0 Control (0x09A8) Bit 0 1 7:2 Description ECAT PDI Reset Value Latch0 positive edge: 0: Continuous Latch active 1: Single event (only first event active) r/(w) r/(w) 0 Latch0 negative edge: 0: Continuous Latch active 1: Single event (only first event active) r/(w) r/(w) 0 Reserved, write 0 r/- r/- 0 NOTE: Write access depends upon setting of 0x0980.4.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 116: Register Latch0 Status (0x09AE) Bit 0 1 2 7:3 Description ECAT PDI Reset Value Event Latch0 positive edge. 0: Positive edge not detected or continuous mode 1: Positive edge detected in single event mode only. Flag cleared by reading out Latch0 Time Positive Edge. Event Latch0 negative edge. 0: Negative edge not detected or continuous mode 1: Negative edge detected in single event mode only. Flag cleared by reading out Latch0 Time Negative Edge.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 118: Register Latch0 Time Positive Edge (0x09B0:0x09B3 [0x09B0:0x09B7]) Bit 63:0 Description Register captures System time at the positive edge of the Latch0 signal. ECAT PDI Reset Value r(ack)/- r/ (w ack)* 0 NOTE: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guarantees reading a consistent value. Reading this register from ECAT clears Latch0 Status 0x09AE[0] if 0x0980.4=0.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) Table 120: Register Latch1 Time Positive Edge (0x09C0:0x09C3 [0x09C0:0x09C7]) Bit 63:0 Description Register captures System time at the positive edge of the Latch1 signal. ECAT PDI Reset Value r(ack)/- r/ (w ack)* 0 NOTE: Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guarantees reading a consistent value. Reading this register from ECAT clears Latch0 Status 0x09AF[0] if 0x0980.5=0.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.50.6 SyncManager Event Times Table 122: Register EtherCAT Buffer Change Event Time (0x09F0:0x09F3) Bit 31:0 Description Register captures local time of the beginning of the frame which causes at least one SyncManager to assert an ECAT event ECAT PDI Reset Value r/- r/- 0 NOTE: Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guarantees reading a consistent value.
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TMC8460-BI Datasheet (V100 / 2016-Sep-01) 5.51 ESC Specific Product and Vendor ID Table 125: Register Product ID (0x0E00:0x0E07) Bit 63:0 Description Product ID ECAT PDI Reset Value r/- r/- TMC8460: 0x0000 0000 0100 8460 Table 126: Register Vendor ID (0x0E08:0x0E0F) Bit 31:0 Description ECAT PDI Reset Value Vendor ID: r/- r/- TMC8460: 0x0000 0286 r/- r/- NOTE: Test Vendor IDs have [31:28]=0xE 63:32 Reserved 5.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 5.53 Process Data RAM (0x1000:0xFFFF) The Process Data RAM starts at address 0x1000. The TMC8460 Process Data RAM has a size of 16kBytes. Table 128: Process Data RAM (0x1000:0x4FFF) Bytes ---- Description Process Data RAM ECAT PDI Reset Value (r/w) (r/w) Random/undefined NOTE (r/w): Process Data RAM is only accessible if EEPROM was correctly loaded (register 0x0110.0 = 1).
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 5.53.2 MFCIO Block ECAT Read Data Memory Block (0x4800:0x4823) Data in this memory block is written by the MFCIO block and read by the ECAT master.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6 6.1 MFCIO Block Register and Functional Description MFCIO Block General Information The MFCIO block is a separate independent function block next to the main ESC data path. It connects to the ESC via a configuration interface and a memory bridge. It comes with its own SPI interface (MFC CTRL SPI) to connect to an application controller. Detailed information on the SPI interface protocol and characteristics is given in section 2.3.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) All functional output signals of the MFCIO block are linked to the OP state of the EtherCAT state machine. As long as the actual state is not OP, all functional output states are not driven but in high impedance state. 6.2 MFCIO Block Address Space Overview The MFCIO block provides functionality useful in an embedded system with focus on motor and motion control. Table 133 : MFCIO Block Register Overview Reg. no.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) The table above gives an overview of all MFCIO block registers. Read-only registers are marked blue, registers that are writable (write-only via EtherCAT) are marked red. The register number (Reg. No.) is required for addressing registers via the MFC CTRL SPI interface. When using EtherCAT access, this is not necessary. The column Configuration address (EEPROM) shows the location where each registers configuration byte is stored in the EEPROM.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) When (re)configuring the EEPROM from an EtherCAT master system special care must be taken. Not every master allows writing a category 1 entry to the EEPROM. There are different ways to write this into the EEPROM for automatically loading the MFCIO block configuration at power-up: • Use preprogrammed EEPROMs. • Use a different category, e.g., 2049, first. Then overwrite the upper byte with 0 with a single EEPROM byte write.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 1011 1100 1101 1110 1111 11 12 13 14 15 Before shadow register handling cycle After shadow register handling cycle Trigger at start of MFC PWM cycle Trigger when data value changes Always triggered Copyright © 2016 TRINAMIC Motion Control GmbH & Co.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.5 MFCIO Block Example Configuration and Example XML/ESI File This section provides two examples on how to parameterize the Trinamic MFCIO block for a specific application. It provides examples of the final XML/ESI files. The manual configuration requires the following steps: 1.) Define which functional units and their registers shall be used from ECAT master side set the RegisterEnable-Bits in the respective register configuration.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) Since the reset value of the configuration block is 0x00, the trailing configuration bytes for registers 6 to 43 can be omitted in the EEPROM. Step 2: The memory areas where all register values for the MFC-Block are located are shown below.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) Step 3: Additional to the MFC Block Configuration, the ESI-File contains the configuration for the EtherCAT Slave Controller itself. This configuration is later read from the EEPROM on reset.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) The configuration for the step/direction registers (12-17) with EtherCAT access is straightforward. All writable registers except for 16 – SD_DLY – should be updated when the value changes, their configuration byte is 0x1E. The readable register 13 – SD_SC – can be used with a transparent shadow register and configuration 0x10. This part of the configuration data is 0x1E101E1E001E.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) #x6010 0 32 SD_SC UDINT Step 4: The configuration of the EtherCAT Slave Controller, which is read from the EEPROM, is 0x0502030000000000000000000000.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.6 MFCIO Incremental Encoder Unit The incremental encoder unit allows the decoding of ABN quadrature signals with zero pulse up to a high speed without CPU load. The parameters for the unit are configurable to fit a wide range of quadrature encoders. The internal accumulator works as a 48 bit fixed point value with a 32 bit integer part which is visible through the encoder position register and a 16 bit fractional part which is only used internally.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.6.7 ENC_CONST The encoder constant is a 32-bit fixed-point value that is added to or subtracted from the internal accumulator.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.7 MFCIO SPI Master Unit The SPI Master Unit provides an interface for up to four SPI slaves with a theoretically unlimited datagram length using multiple accesses. Figure 32 - Block structure of SPI Master Unit The basic configuration requires setting the SPI frequency/bit length, the datagram length and the SPI mode (clock polarity and phase).
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 000: Start when data is written into TX register 001: Start on beginning of PWM cycle 010: Start on center of PWM cycle 011: Start on PWM A mark 100: Start on PWM B mark 101: Start on PWM A&B marks 111: Start on single trigger (Bit 15) SPI clock polarity SPI clock phase LSB first Keep CS low after transfer for transfers 9 SPI_STATUS R 8 10 SPI_LENGTH W 8 11 SPI_TIME W 8 Bit 6: Bit 5: Bit 4: Bit 3: over 64bit Bits 1..
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) Bit 3 can be used for datagrams longer than 64 bit. With this bit set, the chip select line is held low after the transmission, allowing more transmissions in the same datagram. Before the last transmission, this bit must be set to 0 again so that the chip select line goes high afterwards, ending the datagram. Bits 1 and 0 define which chip select line (which slave) is used for the next transmission. 6.7.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.8 MFCIO Step Direction Unit The MFC is equipped with a step-direction unit. Programming of the step pulse frequency occurs by writing an accumulation constant to a register. Toggle of the MSB of the accumulation register value generates an internal step pulse of one internal clock cycle. The direction signal is the MSB of the accumulation constant. Therefore, the sign of the accumulation constant defines the direction signal polarity.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 2.1.2 Step Direction Unit Signals Table 143 : MFCIO S/D unit signals Signal STP DIR IRQ_TARGET_REACHED 2.1.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) Table 145 : MFCIO S/D Unit real world unit relations Parameter fCLK [Hz] Value 25 MHz Description / Function clock frequency of step direction unit tCLK [s] fSTEP [Hz] 40 ns clock period length Max. fSTEP [Hz] 12.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.8.2 Step Counter The step counter counts the number of steps, taking the direction into account. This is a read only register. For initialization to zero a configuration bit within the step direction configuration register hast to be written. 6.8.3 Step Target The step target defines the number of steps to be made for the step mode until stop. This register can be overwritten at any time.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.9 MFCIO PWM Unit The MFC is equipped with a tripe pulse width modulation (PWM) block including programmable brake before make (BBM) unit. Both high side and low side control signals are available as separate outputs. A single PWM counter generates three synchronous PWM signals. Setting the maximum count as limit defines the PWM frequency. Left aligned PWM, Centered PWM, and right aligned PWM is selectable. The BBM take care concerning the BBM timing.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 2.1.4 PWM Unit Signals Table 146 : MFCIO PWM unit signals Signal ES PULSE_ZERO PULSE_A PULSE_CENTER PULSE_B PULSE_AB PWM0_H PWM0_L PWM1_H PWM1_L PWM2_H PWM2_L 2.1.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 25 26 PWM0_CNTRSHFT PWM1_CNTRSHFT W W 16 16 16 27 PWM2_CNTRSHFT W 28 PWM_ PULSE_A W 29 PWM_PULSE_B W 30 PWM_PULSE_LENGTH W 8 31 PWM_BBM_H W 8 32 PWM_BBM_L W 8 16 16 11..0 : These three registers define the shift time for the PWM units, it is intended to create a time gap between PWM edges for phases current measurements (section 6.9.9) 11..0 : This is a programmable ADC trigger pulse A (section 6.9.6) 11..
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) Table 148 : MFCIO PWM block real world unit relations Parameter fCLK[Hz] tCLK[s] max. tPWM[s] Value 100 MHz 10 ns 40,96us min. fPWM[Hz] 24.414 kHz tPULSE_LENGTH tBBM Description / Function clock frequency of PWM unit clock period length Length of PWM period tPWM = tCLK * (1 + PWM_MAXCNT) PWM frequency = 1 / tPWM Comment fCLK[Hz] = 1 / tCLK[s] tCLK[s] = 1 / fCLK[Hz] Maximum tPWM with maximum PWM resolution of 12 bit.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) Figure 39 - Chopper Modes (OFF, Low Side ON, High Side ON, Low Side Chopper, High Side Chopper, Complementary Low Side and high Side Chopper) 6.9.3 PWM_ALIGNMENT Configuration Register This register commonly determines the alignment of the three PWM units. The alignment can be programmed left aligned, centered, or right aligned (pls. refer Figure 36, Figure 37, and Figure 38). Figure 40 - Centered PWM with PWM#2 shifted from Center (Example) 6.9.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.9.5 PWM Value Registers Together with the programmed PWM counter length, the PWM values determine the PWM duty cycle. The PWM duty cycle is individually programmable for each of the three PWM units. Programming the three PWM values sets up a vector of effective three voltages. 6.9.6 PULSE_A Configuration Register The position of the trigger pulse A is programmable within the PWM cycle. A second trigger pulse within the PWM cycle is programmable individually.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.9.13 Emergency Switch Input Off-State The emergency switch input MFC_nES of the TMC8460-BI can be configured to disable the MOSFET power stage immediately, e.g., under control of an external over current comparator (or similar trigger). nES is thereby used as external trigger. It is low active and contains an internal pull down resistor. For normal operation it must be actively pulled high externally.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.10 MFCIO General Purpose IO Unit The MFC GPIO Unit handles the general-purpose inputs and outputs. Eight (8) independent GPIO ports are available. Each GPIO is configurable either as input or as output. 6.10.1 GPIO Registers Three registers are required for MFC GPIO configuration: GPO_OUT_VAL defines the output values of the outputs. GPI_IN_VAL is read only and contains the actual input values. GPIO_CONFIG allows to configure the GPIO direction.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.11 MFCIO Watchdog Unit 6.11.1 General Function The watchdog timer allows monitoring of external signals, or monitoring of ETHERCAT activity. A certain condition can be chosen for retriggering the watchdog, i.e. a certain input signal constellation. In case this constellation does not occur at least once within a pre-programmable time period, the watchdog timer will expire and will trigger a certain watchdog action.
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TMC8460-BI Datasheet (V1.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) Figure 6.42 - Structure of the watchdog unit The following table contains the assignments of ports/signals to the configuration bits in the WD_OUT_MASK_POL register.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) The following table contains the assignments of ports/signals to the configuration bits in the WD_IN_MASK_POL register. Table 153 : Watchdog unit input port configuration assignment Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Signal GPI0 GPI1 GPI2 GPI3 GPI4 GPI5 GPI6 GPI7 SPI_SDO ABN_N ABN_B ABN_A reserved reserved reserved reserved Description WD_IN_POL Bit # 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Copyright © 2016 TRINAMIC Motion Control GmbH & Co.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.12 MFCIO IRQ Unit and Register Set The MFCIO block of the TMC8460 provides a dedicated IRQ output signal to a local microcontroller to indicate certain events and conditions. The pin MFCIO_IRQ can be configured and read out using the two registers shown in the next table.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.13 MFCIO Emergency Switch Input The TMC8460-BI comes with an additional emergency switch input pin. This input pin connects to the MFCIO block. Its function is to indicate an error condition and to switch certain outputs of the MFCIO block into configurable safe states. The emergency switch input is called MFC_nES. It is low active.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 6.15 AL-State Override Configuration All functional output signals of the MFCIO block are linked to the OP state of the EtherCAT state machine. As long as the actual state is not OP, all functional output ports are not driven but in high impedance state. The AL_STATE_OVERRIDE register allows overriding this behavior. The AL_STATE_OVERRIDE register can only be accessed from MFC CTRL SPI interface.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 7 ESD Sensitive Device The TMC8460 is an ESD sensitive CMOS device sensitive to electrostatic discharge. Take special care to use adequate grounding of personnel and machines in manual handling. After soldering the devices to the board, ESD requirements are more relaxed. Failure to do so can result in defect or decreased reliability. 8 Disclaimer TRINAMIC Motion Control GmbH & Co.
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TMC8460-BI Datasheet (V1.00 / 2016-Sep-01) 9 Revision History Version Date Author Description SK= Stephan Kubisch V1.00 2016-Sep-01 SL, SK First release version Table 157: Documentation Revisions Copyright © 2016 TRINAMIC Motion Control GmbH & Co.