Datasheet

TMC6200 DATASHEET (Rev. 1.04 / 2019-AUG-08) 8
www.trinamic.com
Pin
TQFP
Type
Function
LSU
5
Low side gate driver output.
12VOUT
6
Output of internal 11.5V gate voltage regulator and supply pin
of low side gate drivers. Attach 2.2µF to 22µF ceramic
capacitor to GND plane near to pin for best performance. Use
at least 5-10 times more capacity than for bootstrap capacitors.
In case an external gate voltage supply is available, tie VSA
and 12VOUT to the external supply.
5VOUT
7
Output of internal 5V regulator. Attach 2.2µF to 10µF ceramic
capacitor to GNDA near to pin for best performance.
GNDA
8
Analog GND. Connect to GND plane near pin.
CURU
9
AO
Output of current sense amplifier.
CURV
10
AO
Output of current sense amplifier.
CURW
11
AO
Output of current sense amplifier.
VOFS/TEST
12
AI
Center reference for current sense amplifiers (leave open for
5VOUT/3 offset voltage).
CSN_IDRV0
13
DI
SPI chip select input (negative active) (SPE=1) or
Configuration input for gate driver current LSB (SPE=0)
SCK_IDRV1
14
DI
SPI serial clock input (SPE=1) or
Configuration input for gate driver current MSB (SPE=0)
SDI_AMPLx10
15
DI
SPI data input (SPE=1) or
Configuration input for current sense amplifier 5x or 10x
amplification (SPE=0)
SDO_SINGLE
16
DIO
SPI data output (tristate) (SPE=1) or
Configuration input for internal bridge control mode (0: dual
line, 1: xH=phase polarity, xL=phase enable) (SPE=0)
UH
17
DI
(pd)
High side control input (or bridge polarity in single mode)
UL
18
DI
(pd)
Low side control input (or bridge enable in single mode)
VCC_IO
19
3.3V to 5V IO supply voltage for all digital pins.
VH
20
DI
(pd)
High side control input (or bridge polarity in single mode)
VL
21
DI
(pd)
Low side control input (or bridge enable in single mode)
WH
22
DI
(pd)
High side control input (or bridge polarity in single mode)
WL
23
DI
(pd)
Low side control input (or bridge enable in single mode)
CLK
24
DI
CLK input. Tie to GND using short wire for internal clock or
supply external clock. Internal clock-fail over circuit protects
against loss of external clock signal.
SPE
25
DI
(pd)
Mode selection input. When tied low, the chip is in standalone
mode and SPI pins have their configuration pin functions.
When tied high, the SPI interface is enabled. Integrated pull
down resistor.
FAULT
26
DO
Diagnostics output.
High upon driver error condition. Clear by cycling EN.
DRV_EN
27
DI
Positive active enable input. The power stage becomes
switched off (all motor outputs floating) when this pin
becomes driven to a low level. Cycle low to clear FAULT.
VSA
29
Analog supply voltage for 11.5V and 5V regulator. Normally
tied to VS. Provide a 100nF filtering capacitor to GND.
CPO
30
Charge pump capacitor output.