Datasheet

TMC6200 DATASHEET (Rev. 1.04 / 2019-AUG-08) 5
www.trinamic.com
VCC_IO
TMC6200
Configuration
interface
CSN / IDRV0
SCK / IDRV1
SDO / SINGLE
SDI / AMPLx10
Diagnostics
(Short circuit,
Temperature)
5V Regulator
Charge Pump
22n
100V
100n
16V
FAULT
+V
M
5VOUT
VSA
2.2µ
+V
IO
DRV_EN
GNDA
DIE PAD
3.3V or 5V
I/O voltage
100n
100n
3 Phase
Motor
Break before
Make logic
100n
C
E
IU IV
CURV
CURU
CURW
Current Sense
SPE
Enable
B.Dwersteg, ©
TRINAMIC 2014
LS
USENSE
LSU
HSU
U
HS
CU
C
B
+V
M
CPI CPO VCP VS
Gate Voltage
Regulator
12VOUT
4.7µ
470n
pd
pd
unused
0: xH/xL individual gate control
1: xH=Polarity, xL=Enable control
WL
WH
VL
VH
UL
UH
pd
pd
pd
pd
pd
N
S
12VOUT
I
T
VCP
VOFS
LS
VSENSE
LSV
HSV
V
HS
CV
C
B
12VOUT
VCP
LS
WSENSE
LSW
HSW
W
HS
CW
C
B
12VOUT
VCP
I
T
I
T
IV
+
VOFS
IW
+
5VOUT
VOFS
24MHz Oscillator
OTP memory
CLK_IN
+
500k
250k
VOFS
Chopper Control
dual line LS+HS,
or single line
(HS=polarity, LS=enable)
+V
IO
01
Diagnostic Output
Driver Strength [IDRV1 IDRV0]:
00: 0.5A 01: 0.5/1A, 10: 1A, 11: 1.5A
R
S
R1 R2
5VOUT
Use LMV641 or similar
Amplification=1+R2/R1
Figure 1.2 Standalone application using single shunt current sensing
VCC_IO
TMC6200
SPI interface
CSN / IDRV0
SCK / IDRV1
SDO / SINGLE
SDI / AMPLx10
Diagnostics
(Short circuit,
Temperature)
5V Regulator
Charge Pump
22n
100V
100n
16V
FAULT
+V
M
5VOUT
VSA
2.2µ
+V
IO
DRV_EN
GNDA
DIE PAD
3.3V or 5V
I/O voltage
100n
100n
3 Phase
Motor
Break before
Make logic
100n
C
E
IU IV
CURV
CURU
CURW
SPE
B.Dwersteg, ©
TRINAMIC 2014
LS
USENSE
LSU
HSU
U
HS
CU
C
B
+V
M
CPI CPO VCP VS
Gate Voltage
Regulator
12VOUT
4.7µ
470n
pd
pd
WL
WH
VL
VH
UL
UH
pd
pd
pd
pd
pd
N
S
RS
R
P
12VOUT
I
T
VCP
VOFS
LS
VSENSE
LSV
HSV
V
HS
CV
C
B
RS
R
P
12VOUT
VCP
LS
WSENSE
LSW
HSW
W
HS
CW
C
B
RS
R
P
12VOUT
VCP
I
T
I
T
IV
+
VOFS
IW
+
5VOUT
VOFS
24MHz Oscillator
OTP memory
CLK_IN
+
500k
250k
VOFS
+V
IO
SPI
Current SenseEnable
Chopper Control
dual line LS+HS,
or single line
(HS=polarity, LS=enable)
Figure 1.3 SPI mode configuration