Datasheet
TMC5160 DATASHEET (Rev. 1.01 / 2017-NOV-29) 93
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15 STEP/DIR Interface
The STEP and DIR inputs provide a simple, standard interface compatible with many existing motion
controllers. The microPlyer STEP pulse interpolator brings the smooth motor operation of high-
resolution microstepping to applications originally designed for coarser stepping. In case an external
step source is used, the complete integrated motion controller can be switched off. The only motion
controller registers remaining active in this case are the current settings in register IHOLD_IRUN.
15.1 Timing
Figure 15.1 shows the timing parameters for the STEP and DIR signals, and the table below gives
their specifications. When the dedge mode bit in the CHOPCONF register is set, both edges of STEP
are active. If dedge is cleared, only rising edges are active. STEP and DIR are sampled and
synchronized to the system clock. An internal analog filter removes glitches on the signals, such as
those caused by long PCB traces. If the signal source is far from the chip, and especially if the signals
are carried on cables, the signals should be filtered or differentially transmitted.
+VCC_IO
SchmittTrigger
0.44 VCC_IO
0.56 VCC_IO
83k
C
Input filter
R*C = 20ns +-30%
STEP
or DIR
Input
Internal
Signal
DIR
STEP
t
DSH
t
SH
t
SL
t
DSU
Active edge
(DEDGE=0)
Active edge
(DEDGE=0)
Figure 15.1 STEP and DIR timing, Input pin filter
STEP and DIR interface timing
AC-Characteristics
clock period is t
CLK
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
step frequency (at maximum
microstep resolution)
f
STEP
dedge=0
½ f
CLK
dedge=1
¼ f
CLK
fullstep frequency
f
FS
f
CLK
/512
STEP input low time *)
t
SL
max(t
FILTSD
,
t
CLK
+20)
100
ns
STEP input high time *)
t
SH
max(t
FILTSD
,
t
CLK
+20)
100
ns
DIR to STEP setup time
t
DSU
20
ns
DIR after STEP hold time
t
DSH
20
ns
STEP and DIR spike filtering time
*)
t
FILTSD
rising and falling
edge
13
20
30
ns
STEP and DIR sampling relative
to rising CLK input
t
SDCLKHI
before rising edge
of CLK input
t
FILTSD
ns
*) These values are valid with full input logic level swing, only. Asymmetric logic levels will increase
filtering delay t
FILTSD
, due to an internal input RC filter.