Datasheet

TMC5130A DATASHEET (Rev. 1.11 / 2015-OCT-08) 40
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6.4 Encoder Registers
ENCODER REGISTER SET (0X38…0X3C)
R/W
Addr
n
Register
Description / bit names
Range [Unit]
RW
0x38
11
ENCMODE
Encoder configuration and use of N channel
See separate table!
RW
0x39
32
X_ENC
Actual encoder position (signed)
-2^31…
+(2^31)-1
W
0x3A
32
ENC_CONST
Accumulation constant (signed)
16 bit integer part, 16 bit fractional part
X_ENC accumulates
+/- ENC_CONST / (2^16*X_ENC) (binary)
or
+/-ENC_CONST / (10^4*X_ENC) (decimal)
ENCMODE bit enc_sel_decimal switches
between decimal and binary setting.
Use the sign, to match rotation direction!
binary:
± [µsteps/2^16]
±(0 …
32767.999847)
decimal:
±(0.0 …
32767.9999)
reset default =
1.0 (=65536)
R+C
0x3B
1
ENC_STATUS
bit 0: n_event
1: Encoder N event detected. Status bit is
cleared on read: Read (R) + clear (C)
This bit is ORed to the interrupt output
signal.
R
0x3C
32
ENC_LATCH
Encoder position X_ENC latched on N event