Datasheet

TMC5130A DATASHEET (Rev. 1.11 / 2015-OCT-08) 26
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5.2 CRC Calculation
An 8 bit CRC polynomial is used for checking both read and write access. It allows detection of up to
eight single bit errors. The CRC8-ATM polynomial with an initial value of zero is applied LSB to MSB,
including the sync- and addressing byte. The sync nibble is assumed to always be correct. The
TMC5130A responds only to correctly transmitted datagrams containing its own slave address. It
increases its datagram counter for each correctly received write access datagram.
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Hint:
The CRC can be calculated within a CPU using a bit-wise cyclic XOR calculation of incoming and
outgoing bits accumulated to an 8 bit CRC register. You find the algorithm in the TMC5130A-EVAL
evaluation board firmware.
CRC = (CRC << 1) OR (CRC.7 XOR CRC.1 XOR CRC.0 XOR [new incoming bit])
-- CRC.n is meant to extract bit n from the 8 bit CRC register
For a parallel 8 bit calculation of CRC in your CPU, you can use a look-up table. Additional algorithms
can be found in literature.
5.3 UART Signals
The UART interface on the TMC5130A-TA comprises four signals:
TMC5130A UART INTERFACE SIGNALS
SWIOP
Non-inverted data input and output
SWION
Inverted data input and output for use in differential transmission. Can be left open
in a 5V IO voltage system. Tie to the half IO level voltage for best performance in a
3.3V single wire non-differential application.
NAI
Address increment pin for chained sequential addressing scheme
NAO
Next address output pin for chained sequential addressing scheme (reset default=
high)
In UART mode (SW_SEL high) the slave checks the single wire SWIOP and SWION for correctly
received datagrams with its own address continuously. Both signals are switched as input during this
time. It adapts to the baud rate based on the sync nibble, as described before. In case of a read
access, it switches on its output drivers on SWIOP and SWION and sends its response using the same
baud rate.