Datasheet
TMC5130A DATASHEET (Rev. 1.11 / 2015-OCT-08) 10
www.trinamic.com
2 Pin Assignments
2.1 Package Outline
25
26
3724
SWSEL
-
OA2
OA1
-
VS
-
BRA
-
VCP
REFL_STEP
CLK
-
OB1
ENCB_DCEN_CFG4
BRB
OB2
ENCN_DCO
1
TST_MODE
REFR_DIR
VCC_IO
SDO_NAO_CFG0
SDI_NAI_CFG1
SCK_CFG2
CSN_CFG3
SWP_DIAG1
SWN_DIAG0
AIN_IREF
GNDA
CPO
-
SD_MODE
-
VSA
-
2
3
4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21
22
23
36
35
34
33
32
31
30
29
28
27
48
47
46
45
44
43
42
41
40
39
DRV_ENN_CFG6
38
GNDP
13
CPI
VCC
5VOUT
PAD = GNDD
12
SPI_MODE
-
VS
-
ENCA_DCIN_CFG5
-
-
GNDP
TMC5130A-TA
TQFP-48
9mm x 9mm
Figure 2.1 TMC5130A-TA package and pinning TQFP-EP 48 (7x7mm body, 9x9mm with leads)
2.2 Signal Descriptions
Pin
Number
Type
Function
TST_MODE
1
DI
Test mode input. Tie to GND using short wire.
CLK
2
DI
CLK input. Tie to GND using short wire for internal clock or
supply external clock.
CSN_CFG3
3
DI
SPI chip select input (negative active) or configuration input
SCK_CFG2
4
DI
SPI serial clock input and configuration input
SDI_NAI_
CFG1
5
DI
SPI data input and configuration input and next address input for
single wire interface
N.C.
6, 31, 36
Unused pins; connect to GND for compatibility to future versions.
SDO_NAO_
CFG0
7
DIO
SPI data output (tristate) or configuration input or next address
output for single wire interface
REFL_STEP
8
DI
Left reference input when SPI_MODE=1 and SD_MODE=0
STEP input when SD_MODE=1 or SPI_MODE=0