Datasheet

TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28) 20
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5.1 General Configuration Registers
GENERAL CONFIGURATION REGISTERS (0X00…0X1F)
R/W
Addr
n
Register
Description / bit names
RW
0x00
11
GCONF
Bit
GCONF – Global configuration flags
0..2
Reserved, set to 0
3
poscmp_enable
0: Outputs INT and PP are tristated.
1: Position compare pulse (PP) and interrupt output
(INT) are available
Attention – do not leave the outputs floating in tristate
condition, provide an external pull-up or set this bit 1.
4..6
Reserved, set to 0
7
test_mode
0: Normal operation
1: Enable analog test output on pin REFR2
TEST_SEL selects the function of REFR2:
0…4: T120, DAC1, VDDH1, DAC2, VDDH2
Attention: Not for user, set to 0 for normal operation!
8
shaft1
1: Inverse motor 1 direction
9
shaft2
1: Inverse motor 2 direction
10
lock_gconf
1: GCONF is locked against further write access.
R+C
0x01
4
GSTAT
Bit
GSTAT – Global status flags
0
reset
1: Indicates that the IC has been reset since the last
read access to GSTAT.
1
drv_err1
1: Indicates, that driver 1 has been shut down due
to overtemperature or short circuit detection
since the last read access. Read DRV_STATUS1 for
details. The flag can only be reset when all error
conditions are cleared.
2
drv_err2
1: Indicates, that driver 2 has been shut down due
to overtemperature or short circuit detection
since the last read access. Read DRV_STATUS2 for
details. The flag can only be reset when all error
conditions are cleared.
3
uv_cp
1: Indicates an undervoltage on the charge pump.
The driver is disabled in this case.
W
0x03
4
TEST_SEL
Bit
SLAVECONF
3..0
TEST_SEL:
selects the function of REFR2 in test mode:
0…4: T120, DAC1, VDDH1, DAC2, VDDH2
Attention: Not for user, set to 0 for normal operation!
R
0x04
8
+
8
INPUT
Bit
INPUT
0..6
Unused, ignore these bits
7
Reads the state of the DRV_ENN pin
31..
24
VERSION: 0x01=first version of the IC
Identical numbers mean full digital compatibility.