Datasheet

TMC4671 Datasheet • IC Version V1.00 | Document Revision V1.03 • 2018-Sept-06
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Info
Parametrization of fMCLK will be changed in a future version of the chip to match
usual modulator frequencies like 10MHz and 20MHz better. It is recommended to
use a Modulatorfrequency of 25kHz for all applications. If the second ADC group
is not needed, it is recommended to shut it off by setting the MCLK_B register to
0x0.
4.5.0.2 Decimation Configuration MDEC
The high oversampled single bit delta sigma data stream (MDAT) is digitally filtered by Sinc3 filters. To
get raw ADC data, the actual digitally filtered values need to be sampled periodically with a lower rate
called decimation ratio. The decimation is controlled by parameter MDEC_A for ADC group A and MDEC_B
for ADC group B. A new ADC_RAW value is available after MDEC delta sigma pulses of MCLK. As such, the
parameters MCLK and MDEC together define the sampling rate of the 16 bit ADC_RAW values.
The delta sigma modulator with Sinc3 filter works with best noise reduction performance when the length
of the step response time tSINC3 of the Sinc3 filter is equal to the length of the PWM period tPWM =
(PWM_MAXCNT+1) / fPWMCLK = ((PWM_MAXCNT+1) * 10 ns) of the period. The length of the step function
response of a Sinc3 filter is
tSINC3 = (3 · (MDEC − 1) + 1) · tMCLK (7)
MDEC
recommended
=
tPWM
3 · tMCLK
− 2 (8)
fMCLK tMCLK MDEC25 (25 kHz, 40µs) MDEC50 (50 kHz, 20µs) MDEC100 (100 kHz, 10µs)
50 MHz 20 ns 665 331 165
25 MHz 40 ns 331 165 81
20 MHz 50 ns 265 131 65
12.5 MHz 80 ns 165 81 40
10 MHz 100 ns 131 65 31
Table 10: Recommended Decimation Parameter MDEC (equation (8) for different PWM frequencies fPWM
(MDEC25 for fPWM=25kHz w/ PWM_MAXCNT=3999, MDEC50 for fPWM=50kHz w/ PWM_MAXCNT=1999,
MDEC100 for fPWM=100kHz w/ PWM_MAXCNT=999).
Info
Internal structure of the Sinc3 and synchronization to PWM will be enhanced
in future version of the chip. This might need the user’s application controller
software to be changed.
4.5.1 Internal Delta Sigma Modulators - Mapping of V_RAW to ADC_RAW
Generally, delta sigma modulators work best for a typical input voltage range of 25% V_MAX . . . 75% V_MAX.
For the integrated delta sigma modulators, this input voltage operation range is recommended with V_MAX
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