Datasheet

TMC4671 Datasheet • IC Version V1.00 | Document Revision V1.03 • 2018-Sept-06
26 / 158
register function
dsADC_MCFG_B delta sigma modulator configuration MCFG (ANALOG, MCLKI, MCLKO, MDAC), group B
dsADC_MCFG_A delta sigma modulator configuration MCFG (ANALOG, MCLKI, MCLKO, MDAC), group A
dsADC_MCLK_B delta sigma modulator clock MCLK, group B
dsADC_MCLK_A delta sigma modulator clock MCLK, group A
dsADC_MDEC_B delta sigma decimation parameter MDEC, group B
dsADC_MDEC_A delta sigma decimation parameter MDEC, group A
Table 8: Registers for Delta Sigma Configuration
4.5.0.1 Timing Configuration MCLK
When the programmable MCLK is selected, the MCLK_A and MCLK_B parameter registers define the
programmable clock frequency fMCLK of the delta sigma modulator clock signal MCLK for delta sigma
modulator group A and group B. For a given target delta sigma modulator frequency fMCLK, together with
the internal clock frequency fCLK = 100MHz, the MCLK frequency parameter is calculated by
MCLK = 2
31
∗ fMCLK[Hz]/fCLK[Hz] (5)
Due to the 32 bit’s length of the MCLK frequency parameter, the resulting frequency fMCLK might differ
from the desired frequency fMCLK. The back calculation of the resulting frequency fMCLK for a calculated
MCLK parameter with 32 bit length is defined by
fMCLK[Hz] = fCLK[Hz] ∗ MCLK/2
31
(6)
The precise programming of the MCLK frequency is primarily intended for external delta sigma modulators
to meet given EMI requirements. With that, the user can programm frequencies fMCLK with a resolution
better than 0.1 Hz. This advantage concerning EMI might cause trouble when using external delta signal
modulators if they are sensitive to slight frequency alternating. This is not an issue when using external
first-order delta sigma modulators based on R-C-R-CMP (e.g. LM339). But for external second-order delta
signal modulators, it is recommended to configure the MCLK parameter for frequencies fMCLK with kHz
quantization (e.g. 10,001,000 Hz instead of 10,000,001 Hz). Table 9 gives an overview of MCLK parameter
settings for different frequencies fMCLK.
fMCLK_target MCLK fMCLK_resulting comment
25 MHz 0x20000000 25 MHz w/o fMCLK frequency jitter, recommended
20 MHz 0x19000000 20 MHz -468750 Hz recommended for ext. ∆Σ modulator
20 MHz 0x19999999 20 MHz -0.03 Hz might be critical for ext. ∆Σ modulator
12.5 MHz 0x10000000 12.5 MHz w/o fMCLK frequency jitter, recommended
10 MHz 0x0CCCCCCC 10 MHz -0.04 Hz might be critical for ext. ∆Σ modulator
10 MHz 0x0CC00000 10 MHz -39062.5 Hz recommended for ext. ∆Σ modulator
Table 9: Delta Sigma MCLK Configurations
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