Datasheet

TMC4671 Datasheet • IC Version V1.00 | Document Revision V1.03 • 2018-Sept-06
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Figure 8: SPI Timing
SPI Interface Timing Characteristics, fCLK = 25MHz
Parameter Symbol Condition Min Typ Max Unit
SCK valid before or after change of nSCS t
CC
62.5 ns
nSCS high time t
CSH
62.5 ns
nSCS low time t
CSL
62.5 ns
SCK high time t
CH
62.5 ns
SCK low time t
CL
62.5 ns
SCK low time t
CL
62.5 ns
SCK frequency f
SCK
8 MHz
MOSI setup time before rising edge of SCK t
DU
62.5 ns
MOSI hold time after falling edge of SCK t
DH
62.5 ns
MISO data valid time after falling edge of SCK t
DO
10 ns
Table 2: SPI Timing Parameter
Info
The SPI in the TMC4671-ES shows following error: During transaction of read data
the MSB (Bit#31) might get corrupted. This shows in two different ways. The
first one being a 40 ns pulse (positive or negative) on MISO at the beginning of
transfer of that particular bit. This pulse can corrupt the MSB of read data and
this error can be avoided when SPI clock frequency is set to 1 MHz. The second
error also corrupts MSB of read data when MSB of register is unstable. Such as
current measurement noise around zero. In this case, MSB should be ignored
when possible. Please also consider that e.g. actual torque value can be read
from register PID_TORQUE_FLUX_ACTUAL or from INTERIM_DATA register, where
it is showing up in the lower 16 bits. These errors will be fixed in the next IC
version. SPI write access is not affected and can be performed at 8 MHz clock
frequency.
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