Datasheet

TMC4671 Datasheet • IC Version V1.00 | Document Revision V1.03 • 2018-Sept-06
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8 TMC4671 Pin Table
Name Pin IO Description
nRST 50 I active low reset input
CLK 51 I clock input; needs to be 25 MHz for correct timing
TEST 54 I TEST input, must be connected to GND
ENI 55 I enable input
ENO 32 O enable output
STATUS 12 O output for interrupt of CPU (Warning & Status
Change)
SPI_nSCS 6 I SPI active low chip select input
SPI_SCK 7 I SPI clock input
SPI_MOSI 8 I SPI master out slave input
SPI_MISO 9 O SPI master in slave output, high impedance, when
SPI_nSCS = ’1’
UART_RXD 10 I UART receive data RxD for in-system-user commu-
nication channel
UART_TXD 11 O UART transmit data TXD for in-system-user sec-
ondary communication channel
PWM_I 58 I PWM input
DIR 56 I direction input of step-direction interface
STP 57 I step pulse input for step-direction interface
HALL_UX 38 I digital hall input H1 for 3-phase (U) or 2-phase (X)
HALL_V 37 I digital hall input H2 for 3-phase (V)
HALL_WY 36 I digital hall input H3 for 3-phase (W) or 2-phase (Y)
ENC_A 35 I A input of incremental encoder
ENC_B 34 I B input of incremental encoder
ENC_N 33 I N input of incremental encoder
ENC2_A 64 I A input of incremental encoder
ENC2_B 65 I B input of incremental encoder
ENC2_N 66 I N input of incremental encoder
REF_L 67 I Left (L) reference switch
REF_H 68 I Home (H) reference switch
REF_R 69 I Right (R) reference switch
ADC_I0_POS 16 AI pos. input for phase current signal measurement
I0 (I_U, I_X)
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