Datasheet

TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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Read entire documentation; especially the “Supplemental Directives” on page 224.
 MAIN MANUAL 
Because TMC4361A represents the master of SPI communication to the motor driver
– which is the slave – it is mandatory to set up the timing configuration for the SPI
output. TMC4361A provides an SPI clock, which is generated at the SCKDRV_NSDO
output pin.
In order to configure the timing of the SPI clock, set up SPIOUT_CONF
register 0x04 as follows:
Action:
 Set the number of internal clock cycles the serial clock should stay low at
SPI_OUT_LOW_TIME = SPIOUT_CONF (23:20).
 Set the number of internal clock cycles the serial clock should stay high at
SPI_OUT_HIGH_TIME = SPIOUT_CONF (27:24).
 Also, an SPI_OUT_BLOCK_TIME = SPIOUT_CONF (31:28) can be set for a
minimum time period during which no new datagram is sent after the last SPI
output datagram.
Result:
SPI output communication scheme is set. During the inactive phase between to SPI
datagrams - which is at least SPI_OUT_BLOCK_TIME clock cycles long - the
SCKDRV_NSDO and NSCSDRV_SDO pins remain at high output voltage level. The
timing of the SPI output communication is illustrated in the following figure.
Figure 53: SPI Output Datagram Timing
The minimum time period for all three parameters is 2/f
CLK
. If an SPI output parameter
is set to 0, it is altered to 2 clock cycles internally. A maximum time period of 15/f
CLK
can be set for all three parameters.
Thus, SPI clock frequency f
SPI_CLK
covers the following range:
f
CLK
/ 30 ≤ f
SPI_CLK
≤ f
CLK
/ 2.
NSCSDRV_SCLK
SCKDRV_NSDO
SDODRV_SCLK
SDIDRV_NSCLK
bit
CDL-1
bit
CDL-2
bit
0
bit39 bit38 bit0
spi_out_low_time / f
CLK
spi_out_block_time / f
CLK
spi_out_high_time / f
CLK
sample points
Setup of SPI
Output Timing
Configuration
Minimum and
Maximum Time
Period