Datasheet

TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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 MAIN MANUAL 
General IO Timing Parameters
General IO Timing Parameters
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Operation frequency
f
CLK
f
CLK
= 1 / t
CLK
4.2
1)
16
30
MHz
Clock Period
t
CLK
Rising edge to
rising edge
33.5
62.5
ns
Clock time low
16.5
ns
Clock time high
16.5
ns
CLK input signal rise time
t
RISE_IN
20 % to 80 %
20
ns
CLK input signal fall time
t
FALL_IN
80 % to 20 %
20
ns
Output signal rise time
t
RISE_OUT
20 % to 80 %
load 32 pF
3.5
ns
Output signal fall time
t
FALL_OUT
80 % to 20 %
load 32 pF
3.5
ns
Setup time for SPI input
signals in synchronous design
t
SU
Relative to
rising clk edge
5
ns
Hold time
t
HD
Relative to
rising clk edge
5
ns
Table 101: General IO Timing Parameters
1)
The lower limit for f
CLK
refers to the limits of the internal unit conversion to physical units. The chip will also operate at
lower frequencies.