Datasheet

TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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Read entire documentation; especially the “Supplemental Directives” on page 224.
 MAIN MANUAL 
Encoder Registers
R/W
Addr
Bit
Val
Description
W
0x56
15:0
SER_CLK_IN_HIGH (Default: 0x00A0)
U
High voltage level time of serial clock output [# clock cycles].
31:16
SER_CLK_IN_LOW (Default: 0x00A0)
U
Low voltage level time of serial clock output [# clock cycles].
0x57
15:0
SSI_IN_CLK_DELAY (Default: 0x0000)
U
SSI encoder:
Delay time [# clock cycles] between next data transfer after a rising edge of serial
clock output.
i In case SSI_IN_CLK_DELAY = 0:
SSI_IN_CLK_DELAY = SER_CLK_IN_HIGH
SPI encoder: Delay [# clock cycles] at start and end of data transfer between
serial clock output and negated chip select.
i In case SSI_IN_CLK_DELAY = 0:
SSI_IN_CLK_DELAY = SER_CLK_IN_HIGH
31:16
SSI_IN_WTIME (Default: 0x0F0)
U
Delay parameter tw [# clock cycles] between two clock sequences for a multiple
data transfer (of the same data).
i SSI recommendation: tw < 19 µs.
0x58
19:0
SER_PTIME (Default: 0x00190)
U
SSI and SPI encoder: Delay time period tp [# clock cycles] between two
consecutive clock sequences for new data request.
i SSI recommendation: tp > 21 µs.
0x7D
15:0
ENC_COMP_XOFFSET (Default:0x0000)
U
Start offset for triangular compensation in horizontal direction.
0 ≤ ENC_COMP_XOFFSET < 2
16
23:16
ENC_COMP_YOFFSET (Default:0x00)
S
Start offset for triangular compensation in vertical direction.
−128 ≤ ENC_COMP_YOFFSET ≤ 127
31:24
ENC_COMP_AMPL (Default:0x00)
U
Maximum amplitude for encoder compensation.
Table 89: Encoder Registers