Datasheet

TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12
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Read entire documentation; especially the “Supplemental Directives” on page 224.
 MAIN MANUAL 
Pipeline Registers
Shadow Register
Pipeline Register
R/W
Addr
Bit
Val
Description
RW
0x38
31:0
S
X_PIPE0 (Default: 0x00000000): 1
st
pipeline register.
0x39
31:0
S
X_PIPE1 (Default: 0x00000000): 2
nd
pipeline register.
0x3A
31:0
S
X_PIPE2 (Default: 0x00000000): 3
rd
pipeline register.
0x3B
31:0
S
X_PIPE3 (Default: 0x00000000): 4
th
pipeline register.
0x3C
31:0
S
X_PIPE4 (Default: 0x00000000): 5
th
pipeline register.
0x3D
31:0
S
X_PIPE5 (Default: 0x00000000): 6
th
pipeline register.
0x3E
31:0
S
X_PIPE6 (Default: 0x00000000): 7
th
pipeline register.
0x3F
31:0
S
X_PIPE7 (Default: 0x00000000): 8
th
pipeline register.
Table 85: Pipeline Register
Shadow Register
R/W
Addr
Bit
Val
Description
RW
0x40
31:0
S
SH_REG0 (Default: 0x00000000) : 1
st
shadow register.
0x41
31:0
U
SH_REG1 (Default: 0x00000000) : 2
nd
shadow register.
0x42
31:0
U
SH_REG2 (Default: 0x00000000) : 3
rd
shadow register.
0x43
31:0
U
SH_REG3 (Default: 0x00000000) : 4
th
shadow register.
0x44
31:0
U
SH_REG4 (Default: 0x00000000) : 5
th
shadow register.
0x45
31:0
U
SH_REG5 (Default: 0x00000000) : 6
th
shadow register.
0x46
31:0
U
SH_REG6 (Default: 0x00000000) : 7
th
shadow register.
0x47
31:0
S/U
SH_REG7 (Default: 0x00000000) : 8
th
shadow register.
0x48
31:0
U
SH_REG8 (Default: 0x00000000) : 9
th
shadow register.
0x49
31:0
U
SH_REG9 (Default: 0x00000000) : 10
th
shadow register.
0x4A
31:0
U
SH_REG10 (Default: 0x00000000) : 11
th
shadow register.
0x4B
31:0
U
SH_REG11 (Default: 0x00000000) : 12
th
shadow register.
0x4C
31:0
U
SH_REG12 (Default: 0x00000000) : 13
th
shadow register.
0x4D
31:0
U
SH_REG13 (Default: 0x00000000) : 14
th
shadow register.
Table 86: Shadow Register